Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because of the following:
Regarding FIG. 4A: An arrow is missing from step 418 to step 420.
Regarding FIG. 4D: It seems that step 444 is not labeled correctly. See [0046], where no RC check is mentioned. Based on [0043-0047], Examiner believes that the offsets should be applied to rows except for the selected row intended to be read in 442, please confirm and correct if needed.
Regarding FIG. 4E: It seems that the line from 454 to 456 should be “No”. It seems that step 444 is not labeled correctly. See [0047], where no RC check is mentioned. An arrow head should be seen at the end of the line connecting 444 to 414. Based on [0043-0047], Examiner believes that the offsets should be applied to rows except for the selected row intended to be read in 442, please confirm and correct if needed.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Because many problems exist in the specification and the drawings, this application is very difficult to understand. Examiner’s best guess is that a read command to read a selected row or word line is received, then a first read attempt of the selected word line is made, and then at least one other read attempt (a read retry) of the selected word line is made, wherein a voltage level is increased (by applying an offset; see [0043-0047]) on another line (a target line such as another word line or SGS line or a SGD line or a dummy word line) during the read retry. Based on this “best guess” by Examiner, then Examiner suggests amending the specification as follows to clear the confusion and to fix errors:
[0003] Due to malformed contacts, there can be open connections to various row signals within a memory block. In some cases, select gate source (SGS) may not be charged up correctly during erase/program/read operation, leading to different types of failure events. Any sort of broken signal in a return material agreement (RMA) that connects to a NAND word line (WL) can cause a defective part per millions (DPPM) issue. In regards to open row signals, such signals can cause issues with read/verify because the row cannot be put into saturation and thus cannot conduct so all of the cells connected in series with the open row cannot conduct or at the very least do not fully conduct, which causes the rows to appear programmed or at least more programmed, which causes data loss in the case of reads.
[0004] Take SGS open as an example to embody possible failure events in the field. If SGS open occurs at erase, the SGS open will trigger an erase status failure (ESF) event. If SGS open happens during program operation, the SGS open won’t trigger a program status failure (PSF) event because program verification will get a fake pass since the channel won’t conduct anyway . Instead, the SGS open will cause verification of uncorrected error correction code (UECC) during the following read operation. The above two cases can be possibly covered by error handling, so the cases may not be system DPPM. The cases above may still be DPPM concerns for some products without such coverage. A critical issue is if an SGS open occurs during a latent read operation. Since a channel couldn’t be made to conduct via the SGS, multiple WL data (multiple rows of data) loss may occur.
[0005] Moreover, an open location may not necessarily be confined to SGS. Generally, if any of select gate (SG), data or dummy WLs were to be open during a read operation, the channel will be cut off . A plurality of these lines can cause multiple read failures, which can include an open in the SGS line, but can also be an open in the select gate drain (SGD) line. Also an open location can happen in any word line (i.e., data word line, dummy word line, etc.). Any connection to a block can suffer from the kind of problems discussed above. Whenever at least one of these lines is opened, a gate along a data path channel cannot be charged so the channel will be cut off at the location of the gate , which will cause the multiple read failures because memory cells along the entire data path cannot be made to conduct for other WLs. Breaks are not limited to physical breaks but can be electrical breaks as well.
[0007] The present disclosure generally relates to an improved error handling algorithm for data recovery. Rather than running only a default read recovery , an Enhance Read Retry (ERR) algorithm is additionally run. After running a default read recovery, WLs will be flagged with an error flag if the read was unsuccessful. The flag triggers ERR mode.
[0008] In one embodiment, a data storage device comprises a memory device and a controller coupled to the memory device. The controller is configured to read a block of the memory device; determine that a read attempt of a first word line (WL) of the block failed; increase voltage from a first level to a second level on one or more of a select gate drain line (SGD), one or more dummy WLs, one or more data WLs, and a select gate source line (SGS); and retry to read data from the first WL.
[0009] In another embodiment, a data storage device comprises a memory device and a controller coupled to the memory device. The controller is configured to: read a block of the memory device; determine that a read attempt of a first WL of the block failed; trigger RC measurements for the first WL; increase a voltage on one or more of the WLs; and retry to read data from the first WL.
[0010] In yet another embodiment, a data storage device comprises memory means and a controller coupled to the memory means. The controller is configured to: determine that a read failure of one or more WLs of a block of the memory means has occurred; increase a voltage to one or more of the following until either the one or more WLs can be read via a read retry or a maximum voltage has been reached: a SGD; one or more dummy WLs; one or more data WLs; and a SGS.
[0015] Figure 3 is a flow chart illustrating data flow with read retry conditions, according to certain embodiments.
[0019] The present disclosure generally relates to an improved error handling algorithm for data recovery. Rather than running only a default read recovery , an Enhance Read Retry (ERR) algorithm is additionally run. After running a default read recovery, WLs will be flagged with an error flag if the read attempt was unsuccessful. The flag triggers ERR mode.
[0021] Previously, row voltages were static (fixed) on the WLs apart from the WL being read. Additionally, row voltages were kept as low as possible so as to minimize read disturb issues. Also , read error recovery only focused on the WL being read and changing the voltages on that WL. As discussed herein, all three of the previous scenarios are changed such that the host’s data can be recovered quickly. The solutions herein provide a pathway to detecting the problem and allows for the system to take appropriate actions such as block retirement or even die retirement if the problem occurs multiple times. The system can even use the block, with voltage modifications described herein, but it should be noted that continuing to use the block is risky as the defect causing the open WL behavior could degrade to being fully open, resulting in a catastrophic data loss. However, the block could be used for non-critical purposes such as error logging to be able to continue to use the block. Overall, the embodiments discussed herein are a manner of altering the row usage to overcome problems, caused by open rows, in read recovery. If not for the embodiments discussed herein of increasing the voltage or increasing the time or repeatedly pulsing the row signals (or some combination thereof), then there could not be a recovery of the data for the issues and as such would result in a very large amount of data being lost, potentially a full block’s worth of data.
[0024] The host DRAM 138 may optionally include a Host Memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 that is allocated to the data storage device 106 for exclusive use by a controller 108 of the data storage device 106. For example, the controller 108 may store mapping data, buffered commands, logical to physical (L2P) tables, metadata, and the like in the HMB 150. In other words, the HMB 150 may be used by the controller 108 to store data that would normally be stored in a volatile memory 112, a buffer 116, an internal memory of the controller 108, such as static random access memory (SRAM), and the like. In examples where the data storage device 106 does not include a DRAM (i.e., optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM of the data storage device 106.
[0034] Figure 2 is a graph of an analytical model 200 of SGS gate bias, according to certain embodiments. In this example, SGS row (line) is open, it causes consecutive fail events for a few pages, until SGS is fully charged up. Analytical model 200 is of SGS bias change with respect to read numbers (read attempts). Due to the additional RC delay by Rvia and Cvia, SGS charging may be very slow. SGS discharging level should be much less than charging since the pump keeps charging SGS gate during entire WL ramping up clock and WL settling clock, while the pump only discharges the SGS gate by a very short WL ramping down clock. Therefore, the SGS gate will gradually get close to the target bias VSGS (bottom horizontal dash line) by increasing read numbers. So, if the pump drive is enhanced, VSGS should approach the original target more quickly, which means red solid line will exceed blue dash line more easily.
[0035] Figure 3 is a flow chart illustrating a method 300 for data flow with different enhanced read retry methods, according to certain embodiments. In this example data flow always begins with a default read attempt. Method 300 begins at block 302. At block 302, a default read attempt is executed that results in a read failure. The path that begins at block 304 is for a power on reset (POR) method, meaning no changes from default settings. The path that begins at block 306 is the method of increasing read time. The path that begins at block 310 is the method of increasing read bias. It is to be understood that after block 302, method 300 may continue to multiple different paths, the same path multiple times, or a combination of the two. For example, method 300 may take the POR path and the longer time path simultaneously. In another example method 300 may take the longer time path and loop method 300 again and take the same longer wait time path. Another example maybe that method 300 may take the higher bias path and loop method 300 again and take the higher bias path and the POR path. The combinations of paths is infinite after entering ERR mode after default read attempt at block 302.
[0036] After the default read attempt at block 302 method 300 may proceed to block 304. At block 304, a read retry is executed. After the default read attempt at block 302 method 400 may proceed to block 306. At block 306, the row ramping up time or settling time is increased. At block 308, a read retry is executed following the read timing increase. After the default read attempt at block 302 method 300 may proceed to block 310. At block 310, the row bias increase is implemented. At block 312, a read retry is executed after row bias increase is implemented.
[0038] The read flow can also be accelerated by using a means to check all rows at once, rather than running a row RC check, as any broken row can be responsible for the problem, but typically not necessary to know what specific row is responsible for the problem. To implement, one would perform a string sense, with all the rows set to a pass voltage, on the string that has encountered the error. The ones/zeros can be counted (either by a sense amp, or by the system) to see if almost all of the bits read as ones (one being an indicator of a conducting memory hole). If all (or almost all) bits read as one (erased state) then less than likely there would be a broken row problem. Though a row recovery scheme could still be run after exhausting all other recovery routes, for thoroughness.
[0042] There may be a need to increase the time to discharge or take the rows to ground once the recovery process is complete because some signals are shared among certain unselected blocks, on different strings within the same blocks, and possibly in other places in other architectures. If time cannot be added, then the system can wait for a delay and the electrons will dissipate. The unselected blocks share decoder information and are energized at the same time. A problematic row could be an SGS or SGD line and that could cause significant issues when sensing nearby locations, at a minimum, and possibly in sensing any location in other architectures. If there is no discharge of the lines of blocks, then nearby good blocks may be impacted by the lack of time to discharge. The length of the discharge time increase should be proportional to the magnitude of effort needed to make the string conduct as characterized by the methods discussed in the previous paragraphs.
[0043] Increasing the voltage on the neighboring WL during a read may be beneficial to the read operation. For example, if WL90 is being read, WL89 and WL91 might have their pass voltages slightly increased , so as to not interfere with the reading of WL90. Such an offset would likely be in the range of 0.5V to 3V, and that could be reduced or removed if an issue is seen on reading a particular WL. Applying the reduction/removal to the offset can be done [[to]] during all reads. The targeted approach may yield fewer bit errors when reading WLs that do not have impacted neighbors. Thus, yielding better performance in data recovery.
[0044] Figures 4A-4C are flowcharts illustrating a row-by-row check with [[by]] voltage increases. Figures 4D and 4E are flowcharts illustrating an all row check with [[by]] voltage increase. In Figure 4A, the flowchart 400 illustrates the method to start at 402 followed by a read command (a first read attempt) being executed at 404 on a selected row. An error correction code (ECC) issue is encountered at 406 and the standard read recovery flow occurs at 408. A determination is made at 410 regarding whether the read recovery flow was successful. If the read recover flow was successful, then a read retry occurs and is successful at 412 and the method ends at 414. If the read recovery flow is not successful, then a target row or WL is set to the lowest row at 416 followed by applying the control-gate voltage offsets to the target row during another read attempt of the selected row at 418. A determination is then made at 420 regarding the success of the other read attempt. If the read attempt was successful, then the method continues to 412, and ends at 414. If the read attempt was not successful, then the targeted row is increased at 422 followed by a determination regarding whether the targeted row is above the max row at 424. If the targeted row is not above the max row, then the method continues to 418, but if the targeted row is above the max row then the method continues to 426 where the read retry is declared a failure followed by the method ending at 414.
[0045] In Figure 4B, the flowchart 427 is similar to the flowchart 400 of Figure 4A, but after the target row is set to the lowest row at 416, an RC check is run at 428. A determination is then made at 430 regarding whether there is an RC failure. If there is no RC failure, then the method continues to 422. If there is an RC failure, then the target row voltage is increased and the selected row is read at 432 using the increased target row voltage. A determination is then made regarding whether there is a read success at 434. If there is a read success, then the method continues to 412. If there is no read success, then the method continues to 422. In Figure 4C, the flowchart 436 is identical to the flowchart 427 of Figure 4B, except that if there is no read success at 434, the method proceeds to 426 rather than 422.
[0046] In Figure 4D, the flowchart 440 involves an all row check with [[by]] voltage increase. If the recovery is not successful at 410, then a control-gate voltage offset is applied to all unselected rows followed by a read attempt of the selected row at 442. A determination is then made at 444 regarding whether the read attempt was successful. If the read attempt was successful, then the method proceeds to 412, but if the read attempt was [[is]] not successful, then the method proceeds to 426.
[0047] In Figure 4E, a fast all row check is performed with [[by]] voltage increase in flowchart 450. After the ECC issue is encountered at 406, the method involves taking a look at the ones/zeros count at 422 . A determination is made at 454 regarding whether there is an excessive amount of ones or zeros which indicates a possible row failure. Ones and zeros are typically balanced at 50/50. A ratio of 70/30 or even 60/40 could indicate that there is a row failure. If there are no excessive count, then normal read retry occurs at 456 and the method then ends at 414. If there is an excessive count, then the control-gate voltage offsets are applied to all unselected rows and a read attempt of the selected row occurs at 442 followed by the determination at 444 of whether the read attempt is a read success. If there is a read success, then the method ends at 414, but if there is not a read success, then the method proceeds to 456.
[0048] Although Figures 4A-4E show that there can be a bump up of the voltage, there could also be an increase of time, or [[a]] multiple pulses at the same voltage, or a combination of all three, as previously discussed.
Appropriate correction is required.
Claim Objections
Claims 1-20 objected to because of the following informalities:
Regarding claims 1, 11, and 18: The claim is written so broadly because there is no relationship claimed between the claim elements. To advance prosecution, Examiner suggests amending the claim in a way that at least claims some relationship among the claim elements. Also, Applicant seems to want “read” to be mean “read attempt” so Applicant is advised to more accurately claim the invention and clean up grammar while taking into consideration what is Applicant attempting to claim in some of the claims that are also being rejected under 112b for not being definite.
One example of how to amend the claims to at least address grammar and accuracy of the invention is as follows:
Claim 1: A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
read a block of the memory device; and
in response to determining that a read attempt of a first word line (WL) of the block failed[[;]], increase a voltage from a first level to a second level on one or more of:
a select gate drain (SGD);
one or more dummy WLs;
one or more data WLs; and
a select gate source (SGS); and
read data from the first WL.
Claim 11: A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
read a block of the memory device; and
in response to determining that a read attempt of a first word line (WL) of the block failed[[;]],
trigger RC measurements for the first WL[[;]],
increase a voltage on one or more of the WLs[[;]], and
retry to read data from the first WL.
Claim 18: A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
in response to determining that a read attempt failure of one or more word lines (WLs) of a block of the memory means has occurred[[;]],
increase a voltage to one or more of the following until either the one or more WLs can be read or a maximum voltage has been reached:
a selected gate drain (SGS);
one or more dummy WLs;
one or more data WLs; and
a select gate source (SGS).
Claim 2: The data storage device of claim 1, wherein the controller is further configured to retire the block after attempting reading data from the first WL.
Claim 4: The data storage device of claim 1, wherein the controller is further configured to determine to enter enhanced read recovery (ERR).
Claim 6: The data storage device of claim 1, wherein the controller is further configured to determine that a new read attempt of [[a]] the first word line (WL) of the block failed after increasing the voltage to the second level.
Claim 7: The data storage device of claim 6, wherein the controller is further configured to increase the voltage from the second level to a third level on one or more of: the SGD, the one or more dummy WLs, the one or more data WLs, or the SGS.
Claim 9: The data storage device of claim 1, wherein the controller is further configured to perform a string sense to the first WL with all other word lines of the block set to a pass voltage.
Claim 10: The data storage device of claim 1, wherein the controller is further configured to bring all WLs to ground after attempted reading data from the first WL.
Claim 12: The data storage device of claim 11, wherein the controller is further configured to:
determine that a previous read attempt of the first WL has failed; and
retire the block when a number of previous read attempt failures exceeds a threshold.
Claim 14: The data storage device of claim 11, wherein the triggering occurs after attempted reading all WLs of the block.
Claim 20: The data storage device of claim 18, wherein the increasing the voltage occurs after completing a read attempt on each of the WLs of the block.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2, 14 and 20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 2, 14, and 20: The phrase “after reading data” or “after completing a read operation” in plain English includes embodiments, wherein the reading was successful BUT Applicant never redefined “reading” to be limited to only attempted reading and Applicant’s disclosure does not disclose embodiments, wherein a block is retired after successful reading or increasing the voltage after successful reading for all WLs. Hence, the claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-9, and 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4: Applicant did not provide a limiting definition of the term “enhance read recovery (ERR)” so one of ordinary skill in the art can not interpret such a claim with definiteness. Hence, the claim is indefinite. Claim 5 depends on claim 4.
Regarding claim 6: The term “a first word line” causes indefiniteness as to whether this word line is supposed to be the same first word line introduced in claim 1. Claims 7-8 depend on claim 6.
Regarding claim 7: It is indefinite as what level “the level” is to refer to. The antecedent basis is not clear or is indefinite.
Regarding claim 9: It is unclear how a string sense can be performed if ALL rows (all word lines) of the block are set to a pass voltage because a selected word line must have a read voltage applied to it to read from it so the claim does not make sense.
Regarding claim 13: There is insufficient antecedent basis for “the count”. Also, it is unknown what the phrase “map WLs back to common signals” means.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2015/0003169) in view of Chen (US 2020/0211653).
Regarding claim 1: Nam (FIG. 1, FIG. 20-21) teaches a data storage device, comprising:
a memory device (110 in FIG. 1); and
a controller (140 in FIG. 1) coupled to the memory device, wherein the controller is configured to:
read a block of the memory device (a block is illustrated in FIG. 21; [0160-0166]), wherein a first word line (WL) of the block is read by applying a read pass voltage (Vread) at a first level to one or more of following lines:
a select gate drain (SGD) (SSL1);
one or more dummy WLs (SDWL1 and SDWL2);
one or more data WLs (at least one word line among WL1-m); and
a select gate source (SGS) (GSL); and
read data from the first WL (see FIG. 20 and “a sensing operation may be performed”).
Nam does not specifically teach the following:
determine that a read of the WL of the block failed; and
Increase a voltage from the first level to a second level one or more of the above lines.
Chen ([0050, 0059] and Claim 1) teaches increasing the read pass voltage value in response to determining that the selected page comprises the memory cell having a first error and the memory cell having a second error, and increasing the read pass voltage value in response to determining that the selected page comprises the memory cell having the second error but does not comprise the memory cell having the first error
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Chen into the device and/or method of Nam in a manner such that a read of the WL of the block would be determined to have failed such as determining that the selected page comprises the memory cell having the second error of Chen but does not comprise the memory cell having the first error of Chen, and then a pass voltage would be increased from a first level to a second level on one or more of the lines since Chen already teaches applying the same pass voltage to all of the above lines (SSL1, SDWL1, SDWL2, GSL). Note, that when reading the upper most word line of a block, SDWL2 or SSL2 may be an adjacent word line, when the memory block does not have dummy word lines, which are known by one of ordinary skill in the art to be optional, then SSL and GSL lines become adjacent lines at times. The motivation to do so would have been to make read retry attempts in response to the detection of at least one read error as exemplified by Chen.
Regarding claim 3: Nam as modified above taches the data storage device of claim 1, wherein increasing the voltage comprises increasing the voltage on the SGD, the one or more dummy WLs, the one or more data WLs, and the SGS (see Nam, wherein the read pass voltage is applied to all of these lines, and is increased in the modification by Chen).
Regarding claim 9: In so far as definite Nam teaches the data storage device of claim 1, wherein the controller is further configured to perform a string sense to the first WL with all rows of the block set to a pass voltage (FIG. 21; all lines are at Vread).
Regarding claim 10: Nam teaches the data storage device of claim 1, wherein the controller is further configured to bring all WLs to ground after reading data from the first WL (Nam teaches in FIG.s 6-14 performing a recovery period at the end of each read operation, wherein all WLs are driven to ground).
Claim(s) 11 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (US 2015/0301885) and Zhan et al. (US 2022/0293182).
Regarding claim 11: Yuan (FIG. 5A; [0099-0104]) teaches a data storage device, comprising:
a memory device (126 in FIG. 1B); and
a controller (110 in FIG. 1B) coupled to the memory device, wherein the controller is configured to:
read a block of the memory device (502 or 508);
determine that a read of a first word line (WL) of the block failed (510);
increase a voltage on one or more of the WLs (513);
read data from a first WL (508).
Yuan does not specifically teach a controller configured to trigger RC measurements for the first WL.
Zhan ([0067-0068]; FIG. 6) teaches a controller can perform word line RC measurements to calibrate trim values to be utilized in read operations or the controller may look up the estimated RC time constant of the word line in a lookup table mapping RC time constant values to the charging times. Also, Zhan teaches charging (increasing voltage) and discharging (reducing voltage) of a selected word line during a read operation in FIG. 6 based on RC measurements.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Zhan into the device and/or method of Yuan in a manner such that the controller would be configured to trigger RC measurements for the first WL. The motivation to do so would have been to perform word line RC measurements to calibrate trim values to be utilized in read operations as taught by Zhan.
Regarding claim 15: Yuan as modified above teaches the data storage device of claim 11, wherein the increasing of the voltage occurs based upon retrieving voltage increase information from a predefined table ([0068] of Zhan).
Regarding claim 16: Yuan as modified above teaches the controller is further configured to discharge the one or more WLs (FIG. 6 of Zhan).
Regarding claim 17: Yuan as modified above teaches the data storage device of claim 11, wherein the controller is further configured to increase a sense period of time for reading the first WL (increase relative to what was not claimed; in the modification above, if an RC time constant for a selected word line is greater than normal or of that of another word line then the pre-charge time for the selected word line would be set to be greater; thus, increasing the sense period of time; see [0068] and FIG. 6 of Zhan).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (US 2015/0301885) as modified by Zhan (US 2022/0293182), and further in view of Coulson (US 2007/0294588).
Regarding claim 12: Yuan as modified above teaches the controller is configured to determine that a previous read the first WL has failed (512 in FIG. 5A of Yuan).
Yuan as modified above does not specifically teach the controller is further configured to retire the block when a number of previous failures exceeds a threshold.
Coulson (FIG. 2; [0029]; claim 27) teaches a controller configured to retire a block when a number of previous failures (a number of read errors) exceeds a threshold.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Coulson into the device and/or method of Yuan as modified above in a manner such that the controller would be configured to retire a block when a number of previous failures (a number of read errors) exceeds a threshold. The motivation to do so would have been to identify a block as defective or bad.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nam (US 2015/0003169) in view of Chen (US 2020/0211653) and Yuan (US 2015/0301885).
Regarding claim 18: Nam (FIG. 1, FIG. 20-21) teaches a data storage device, comprising:
[a] memory means (110 in FIG. 1); and
a controller (140 in FIG. 1) coupled to the memory device, wherein the controller is configured to:
read a block of the memory device (a block is illustrated in FIG. 21; [0160-0166]), wherein a first word line (WL) of the block is read by applying a read pass voltage (Vread) at a first level to one or more of following lines:
a select gate drain (SGD) (SSL1);
one or more dummy WLs (SDWL1 and SDWL2);
one or more data WLs (at least one word line among WL1-m); and
a select gate source (SGS) (GSL).
Nam does not specifically teach the following:
determining that a read of a first word line (WL) of the block failed;
determine that a read failure of one or more word lines (WLs) of a block of the memory means has occurred; and
increase a voltage to one or more of the lines cited above.
Chen ([0050, 0059] and Claim 1) teaches increasing the read pass voltage value in response to determining that the selected page comprises the memory cell having a first error and the memory cell having a second error, and increasing the read pass voltage value in response to determining that the selected page comprises the memory cell having the second error but does not comprise the memory cell having the first error
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Chen into the device and/or method of Nam in a manner such that a read of the WL of the block would be determined to have failed such as determining that the selected page comprises the memory cell having the second error of Chen but does not comprise the memory cell having the first error of Chen, and then a pass voltage would be increased from a first level to a second level on one or more of the lines since Chen already teaches applying the same pass voltage to all of the above lines (SSL1, SDWL1, SDWL2, GSL). Note, that when reading the upper most word line of a block, SDWL2 or SSL2 may be an adjacent word line, when the memory block does not have dummy word lines, which are known by one of ordinary skill in the art to be optional, then SSL and GSL lines become adjacent lines at times. The motivation to do so would have been to make read retry attempts in response to the detection of at least one read error as exemplified by Chen.
Nam as modified above does not specifically teach increase a voltage to one or more of the lines cited above until either the one or more WLs can be read or a maximum voltage has been reached.
Yuan (FIG. 5A and [0186-0188]) teaches increasing a voltage to one or more word lines until the one or more WLs can be read or a maximum volage has been reached.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Yuan into the device and/or method of Nam as modified by Chen in a manner such that a voltage to one or more of the lines cited above would be increased until either the one or more WLs can be read or a maximum voltage has been reached. The motivation to do so would have been to continue executing read attempts until a successful read (possibly one with correctable errors; see 510 in FIG. 5A of Yuan) or a maximum number of attempts has been reached.
Regarding claim 19: Nam as modified above taches the data storage device of claim 18, wherein the increasing the voltage occurs after performing a read recovery operation (at the end of each read attempt Nam teaches a recovery period; see FIGs. 6-14; hence, the next read attempt in the modified embodiment, wherein a voltage is increased until a read success or a maximum voltage is reached, occurs after performing a read recovery of the previous read attempt).
Regarding claim 20: In so far as definite Nam as modified above teaches the data storage device of claim 18, wherein the increasing the voltage occurs after completing a read operations (after an attempted read of a word line) for all WLs of the block (at the end of each read attempt Nam teaches a recovery period; see FIGs. 6-14; hence, the next read attempt in the modified embodiment, wherein a voltage is increased until a read success or a maximum voltage is reached, occurs after performing a read attempt and a read recovery of the previous read attempt).
Conclusion
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827