Prosecution Insights
Last updated: April 19, 2026
Application No. 18/355,111

NAND DIE WITH WIRE-BOND INDUCTIVE COMPENSATION FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES

Non-Final OA §102§103
Filed
Jul 19, 2023
Examiner
SUN, YU-HSI DAVID
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sandisk Technologies Inc.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
85%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
648 granted / 845 resolved
+8.7% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
27 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
45.9%
+5.9% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
16.6%
-23.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 845 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4, 5, 8, 10, 11, 14, 15, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHOI (US PG Pub 2020/0381399, hereinafter Choi). Regarding claim 1, figure 1 of Lin discloses a storage device, comprising: a substrate (100) of a memory package that includes a first pin pad (200); a controller (¶80-85 and Fig 1, 350) mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel (¶ 80-85 and Fig. 12-13); and a first memory die (360, ¶80-85), comprising: a front pin pad (600, furtherst away left side) electrically connected to the first pin pad of the substrate by way of a first bond wire (900,¶ 31); a rear pin pad (600, second closest to the right side); a first conductor segment (Fig 1-2, 760, ¶ 51) electrically connecting the front pin pad (600, furtherst away left side) and the rear pin pad (600, second closest to the right side) of the first memory die; and a plurality of memory cells 300S, ¶ 80-85 teaching the memory and controllers of Fig 12-13 applying to any prior embodiment) configured to provide non-volatile storage accessible by way of the data channel (¶ 80-85). Regarding claim 4, figure 1 of Choi discloses the rear pin pad (250a) is electrically connected to a pin pad of a second memory die (300S) by way of a second bond wire (900, ¶31), thereby extending the data channel to at least the second memory die (¶ 80-85). Regarding claim 5, Choi discloses the first conductor segment introduces an additional impedance on a segment of the channel between the front pin pad and the rear pin pad of the first memory die of at least 100 picohenry (pH)(¶ 65 and see Fig. 9). Regarding claim 8, figure 1 of Choi discloses the plurality of memory cells are electrically connected to the data channel by way of the rear pin pad of the first memory die (300S and furthest pin pads are all connected, ¶ 80-85). Regarding claim 10, figure 1 of Choi discloses the front (600 furthest away left side) and rear (600 second closest to the right side) pin pads and the first conductor segment (760, ¶ 51) are formed on a top surface of the first memory die (360), wherein the first conductor segment is a conductor land. Regarding claim 11, figure 1 of Choi discloses the entire claimed invention as noted in the above rejections (see claims1 and 10). Regarding claims 14-15, and 18, figure 1 of Choi discloses the entire claimed invention as noted in the above rejections. Regarding claim 20, figure 1 of Choi discloses the entire claimed invention as noted in the above rejections (see claims1 and 10). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 6-7, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Choi. Regarding claims 6 and 16, Choi does not explicitly disclose the additional impedance on the segment is between 300 and 500 picohenry (pH). However, it would have been obvious to form the device so the additional impedance is within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claims 7 and 17, Choi does not explicitly disclose the first conductor segment defines a conductor having a length of between 200 microns and 350 microns and a conductor width between 3 microns and 15 microns. However, it would have been obvious to form the first conductor segment with dimensions within the claimed ranges, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Allowable Subject Matter Claims 2-3, 9, 12, 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU-HSI D SUN/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jul 19, 2023
Application Filed
Dec 28, 2025
Non-Final Rejection — §102, §103
Apr 09, 2026
Applicant Interview (Telephonic)
Apr 09, 2026
Examiner Interview Summary

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
85%
With Interview (+8.4%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 845 resolved cases by this examiner. Grant probability derived from career allow rate.

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