DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to Applicant’s Communication of application S/N 18/355,331 filed on July 19, 2023. Claims 1 to 20 are currently pending with the application.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites the limitation “each input layout file” in line 6, which appears to contain a typographical error, and that should read “the input layout file”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “a first block configured to”, “a second block configured to”, “a third block configured to”, recited in claims 12 to 20.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. (See Specification Para [0040] – “some or all of the elements of matching system 300b may be implemented on a computing device, such as a computer, workstation, tablet, smartphone or other similar computing device.”)
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 to 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitations “a first block configured to designate a previously identified wafer hotspot in an input layout file that comprises a portion of an integrated circuit layout, wherein the input layout file includes a hotspot label that designates the previously identified wafer hotspot” in line 1. These limitations are not clear. More specifically, it is not clear what is the intention of the limitation “a first block configured to designate a previously identified wafer hotspot in an input layout file that comprises a portion of an integrated circuit layout”, where the limitation further recites “wherein the input layout file includes a hotspot label that designates the previously identified wafer hotspot”, which appears to indicate that the wafer hotspot has been previously designated. That is, it is not clear what the “designate” operation of the first block entails, since the hotspot appears to be received already “designated”, therefore, rendering the claim indefinite. Same rationale applies to claim 18, since it recites similar limitations, and to claims 13 to 17, 19, and 20, since they inherit the same deficiencies, by virtue of their dependency.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 to 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claims 1, 12, and 18 recite matching a wafer hotspot to categories.
The limitation of matching a wafer hotspot to categories, which specifically recites “match the previously identified wafer hotspot to one of a plurality of categories of wafer hotspot types”, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind, but for the recitation of generic computer components. That is, other than reciting “by at least one processor”, nothing in the claim element precludes the steps from practically being performed in a human mind. For example, but for the “by at least one processor” language, “matching”, in the context of this claim encompasses the user mentally, with the aid of pen and paper, identifying a category of wafer hotspot that corresponds to the previously identified wafer hotspot. If a claim limitation, under its broadest reasonable interpretation, covers mental processes but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claims recite an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claims recite the additional elements – “receive an input layout file that comprises a portion of an integrated circuit layout that includes a previously identified wafer hotspot, wherein each input layout file includes a hotspot label that designates the previously identified wafer hotspot”, “convert information from the input layout file to generate an image of the portion of the integrated circuit layout with the previously identified wafer hotspot, wherein the image comprises TIFF, BMP, JPG, JPEG or PNG data”, “apply a machine learning model to the image data”, “output a proposed layout modification associated with the matching category of wafer hotspot types”, “designate a previously identified wafer hotspot in an input layout file that comprises a portion of an integrated circuit layout”, at least one processor, a memory, and a machine learning model. The limitations “receive an input layout file that comprises a portion of an integrated circuit layout that includes a previously identified wafer hotspot, wherein each input layout file includes a hotspot label that designates the previously identified wafer hotspot”, and “output a proposed layout modification associated with the matching category of wafer hotspot types” amount to data-gathering steps which is considered to be insignificant extra-solution activity (See MPEP 2106.05(g)).
Continuing with the analysis, the limitations “designate a previously identified wafer hotspot in an input layout file that comprises a portion of an integrated circuit layout” and “convert information from the input layout file to generate an image of the portion of the integrated circuit layout with the previously identified wafer hotspot, wherein the image comprises TIFF, BMP, JPG, JPEG or PNG data” are recited at a high-level of generality, with no restriction on how the result is accomplished and no description of the mechanism for accomplishing the result, and is equivalent to merely saying “applying it”. The limitation “apply a machine learning model to the image data” is recited at a high-level of generality, and amounts to no more than mere instructions to apply the exception using generic computer components, because it does no more than invoking computers or other machinery merely as a tool to perform an existing process. The at least one processor, a memory, and a machine learning model in these steps is recited at a high-level of generality (i.e., as a generic processor performing a generic computer function) such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. The insignificant extra-solution activity identified above, which include the data gathering steps, is recognized by the courts as well-understood, routine, and conventional activity when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity (See MPEP 2106.05(d)(II)(i) Receiving or transmitting data over a network, e.g., using the Internet to gather data, buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network)). The claims are not patent eligible.
Claim 2 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 2 recites the same abstract idea of claim 1. The claim recites the additional limitations of “the input layout file comprises a label that designates the previously identified wafer hotspot”, which is tying the abstract idea to a field of use by further specifying the target data, and which is simply an attempt to limit the application of the abstract idea to a particular technological environment; merely indicating a field of use or technological environment in which to apply the judicial exception does not meaningfully limit the claim (See MPEP 2106.05(h)). Same rationale applies to claims 3 to 5, 8, and 9.
Claim 6 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 6 recites the same abstract idea of claim 1. The claim recites the additional limitations of “the machine learning system comprises a convolutional neural network”, which is recited at a high-level of generality, and amounts to no more than mere instructions to apply the exception using generic computer components, because it does no more than invoking computers or other machinery merely as a tool to perform an existing process. Additional elements that invoke computers, computer components, or other machinery in its ordinary capacity, merely as a tool, or simply add a general-purpose computer or computer components after the fact to an abstract idea, do not integrate a judicial exception into a practical application nor provide significantly more. Same rationale applies to claim 7.
Claim 10 is dependent on claim 1 and includes all the limitations of claim 1. Therefore, claim 10 recites the same abstract idea of claim 1. The claim recites the additional limitations of “the machine learning system comprises a machine learning model trained to match previously identified wafer hotspots to one of N categories of wafer hotspots”, which is recited at a high-level of generality, with no restriction on how the result is accomplished and no description of the mechanism for accomplishing the result, and is equivalent to merely saying “applying it”, therefore, does not integrate the judicial exception into a practical application nor amount to significantly more. Same rationale applies to claim 11.
Additionally, the claims do not include a requirement of anything other than conventional, generic computer technology for executing the abstract idea, and therefore, do not amount to significantly more than the abstract idea.
Same rationale applies to claims 13 to 17, 19, and 20 since they recite similar limitations.
Claims 1 to 20 are therefore not drawn to eligible subject matter as they are directed to an abstract idea without significantly more.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 to 6, and 8 to 11 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (U.S. Publication No. 2019/0213725) hereinafter Liang, in view of LEU et al. (U.S. Publication No. 2020/0026819) hereinafter Leu, and further in view of Kwang et al. (U.S. Publication No. 2009/0268958) hereinafter Kwang.
As to claim 1:
Liang discloses:
A system comprising: at least one processor; and a memory storing instructions that when executed by the at least one processor cause the system to:
receive an input layout file that comprises a portion of an integrated circuit layout that includes a previously identified wafer hotspot, wherein each input layout file includes a hotspot label that designates the previously identified wafer hotspot [Paragraph 0006 teaches receiving a defect list and a circuit layout image; Paragraph 0007 teaches receiving a defect list and a circuit layout image; Paragraph 0033 teaches circuit layout image is a circuit design chart corresponding to the circuit board under inspection];
convert information from the input layout file to generate an image of the portion of the integrated circuit layout with the previously identified wafer hotspot [Paragraph 0007 teaches generating a first cropped defect image based on defect location according to the circuit layout image, therefore, generating an image of the portion of the integrated circuit layout with the previously identified defect];
apply a machine learning model to the image data to match the previously identified wafer hotspot to one of a plurality of categories of wafer hotspot types [Paragraph 0007 teaches defect classifying module inputs the first cropped defect image to a defect classifying model; Paragraph 0038 teaches input the first cropped defect image to a defect classifying model for classification into a type of defect, therefore, matching the hotspot to one of a plurality of categories; Paragraph 0041 teaches classifier determines to which defect type the defect belongs].
Liang does not appear to expressly disclose wherein the image comprises TIFF, BMP, JPG, JPEG or PNG data; and output a proposed layout modification associated with the matching category of wafer hotspot types.
Leu discloses:
the image comprises TIFF, BMP, JPG, JPEG or PNG data [Paragraph 0031 teaches defect data will be processed to be JPG, TIFF, PNG; Paragraph 0039 teaches the file format of defect image is different with the file format of design layout pattern, i.e., JPEG; Paragraph 0015 teaches defect layout pattern groups file information in the design layout pattern coordinate regions are converted to systematic defect text and image data file].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of the cited references and modify the invention as taught by Liang, by incorporating images comprising TIFF, BMP, JPG, JPEG or PNG data, as taught by Leu [Paragraph 0031, 0039], because both applications are directed to identification and classification of defects in wafers; incorporating images specifically of a certain format, as opposed to a different image format is a simple substitution of one known element for another to obtain predictable results.
Neither Liang nor Leu appear to expressly disclose output a proposed layout modification associated with the matching category of wafer hotspot types.
Kwang discloses:
output a proposed layout modification associated with the matching category of wafer hotspot types [Paragraph 0052 teaches matching pattern clips in the layout, and retrieve correction guidance descriptions associated with the matched pattern, where the correction guidance descriptions are to remove the hotspot in the layout or to reduce the hotspot severity; Paragraph 0014 teaches determining a set of correction recommendations when the pattern matches a known manufacturing hotspot].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of the cited references and modify the invention as taught by Liang, by output a proposed layout modification associated with the matching category of wafer hotspot types, as taught by Kwang [Paragraph 0052, 0014], because the applications are directed to identification and classification of defects in wafers; determining and providing layout modifications improves manufacturability of the designs (See Kwang Para [0041]).
As to claim 2:
Liang discloses:
the input layout file comprises a label that designates the previously identified wafer hotspot [Paragraph 0006 teaches receiving a defect list and a circuit layout image; Paragraph 0007 teaches receiving a defect list and a circuit layout image; Paragraph 0033 teaches circuit layout image is a circuit design chart corresponding to the circuit board under inspection].
As to claim 3:
Liang as modified by Leu discloses:
the image file comprises a Graphic Design System data file [Paragraph 0096 teaches the design layout pattern format can be GDS format, GDS-II format, etc.].
As to claim 4:
Liang discloses:
each of the categories of wafer hotspot types comprises a corresponding category indicator [Paragraph 0038 teaches types of defects include, for example, dander, dust, incomplete release of a film, normal, broken circuit, short circuit, etc.].
As to claim 5:
Liang as modified by Leu discloses:
each of the categories of wafer hotspot types comprises a corresponding text description of the proposed layout modification [Paragraph 0121 teaches defect pattern library and frequent failure defect library, including text descriptions; Fig. 9, 1610-1630 teach descriptions of the layouts].
As to claim 6:
Liang discloses:
the machine learning system comprises a convolutional neural network [Paragraph 0039 teaches the defect classification model is a convolutional neural network model].
As to claim 8:
Liang as modified by Leu discloses:
the output comprises text [Paragraph 0097 teaches obtaining the defect text data].
As to claim 9:
Liang as modified by Leu discloses:
the output comprises an image [Paragraph 0097 teaches obtaining the defect image].
As to claim 10:
Liang discloses:
the machine learning system comprises a machine learning model trained to match previously identified wafer hotspots to one of N categories of wafer hotspots [Paragraph 0038 teaches classifying the cropped defect image using a classifying model, into a type of defect, including, for example, dander, dust, incomplete release of a film, normal, broken circuit, short circuit, etc.].
As to claim 11:
Liang discloses:
a graphical user interface configured to facilitate training and implementation of the machine learning system [Paragraph 0021 teaches physical components, such as a keyboard, a mouse, a touch panel, etc., may also be used together, so as to receive the user’s operation].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (U.S. Publication No. 2019/0213725) hereinafter Liang, in view of LEU et al. (U.S. Publication No. 2020/0026819) hereinafter Leu, in view of Kwang et al. (U.S. Publication No. 2009/0268958) hereinafter Kwang, and further in view of AMTHOR et al. (U.S. Publication No. 2023/0111345) hereinafter Amthor.
As to claim 7:
Liang does not appear to expressly disclose the machine learning system comprises an image-to-image translation predictor.
Amthor discloses:
the machine learning system comprises an image-to-image translation predictor [Paragraph 0068 teaches image-to-image transformation can then be carried out using a machine-learned algorithm].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of the cited references and modify the invention as taught by Liang, by incorporating an image-to-image translation predictor, as taught by Amthor [Paragraph 0068], because the applications are directed to identification and classification of defects; incorporating an image-to-image translation predictor to perform the clustering or matching of the images is a simple substitution of one known element for another to obtain predictable results.
Claims 12 to 17 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (U.S. Publication No. 2019/0213725) hereinafter Liang, and further in view of LEU et al. (U.S. Publication No. 2020/0026819) hereinafter Leu.
As to claim 12:
Liang discloses:
An apparatus comprising: a first block configured to designate a previously identified wafer hotspot in an input layout file that comprises a portion of an integrated circuit layout, wherein the input layout file includes a hotspot label that designates the previously identified wafer hotspot [Paragraph 0006 teaches receiving a defect list and a circuit layout image; Paragraph 0007 teaches receiving a defect list and a circuit layout image; Paragraph 0033 teaches circuit layout image is a circuit design chart corresponding to the circuit board under inspection];
a second block configured to convert information from the input layout file to generate an image of the portion of the integrated circuit layout with the previously identified wafer hotspot [Paragraph 0007 teaches generating a first cropped defect image based on defect location according to the circuit layout image, therefore, generating an image of the portion of the integrated circuit layout with the previously identified defect];
a third block comprising a machine learning model configured to match the previously identified wafer hotspot to one of a plurality of categories of wafer hotspot types [Paragraph 0007 teaches defect classifying module inputs the first cropped defect image to a defect classifying model; Paragraph 0038 teaches input the first cropped defect image to a defect classifying model for classification into a type of defect, therefore, matching the hotspot to one of a plurality of categories; Paragraph 0041 teaches classifier determines to which defect type the defect belongs].
Liang does not appear to expressly disclose wherein the image comprises TIFF, BMP, JPG, JPEG or PNG data.
Leu discloses:
the image comprises TIFF, BMP, JPG, JPEG or PNG data [Paragraph 0031 teaches defect data will be processed to be JPG, TIFF, PNG; Paragraph 0039 teaches the file format of defect image is different with the file format of design layout pattern, i.e., JPEG; Paragraph 0015 teaches defect layout pattern groups file information in the design layout pattern coordinate regions are converted to systematic defect text and image data file].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of the cited references and modify the invention as taught by Liang, by incorporating images comprising TIFF, BMP, JPG, JPEG or PNG data, as taught by Leu [Paragraph 0031, 0039], because both applications are directed to identification and classification of defects in wafers; incorporating images specifically of a certain format, as opposed to a different image format is a simple substitution of one known element for another to obtain predictable results.
As to claim 13:
Liang as modified by Leu discloses:
the image file comprises a Graphic Design System data file [Paragraph 0096 teaches the design layout pattern format can be GDS format, GDS-II format, etc.].
As to claim 14:
Liang as modified by Leu discloses:
the image comprises TIFF, BMP, JPG, JPEG or PNG data [Paragraph 0090 teaches defect data will be processed to be JPG, TIFF, PNG, image data file, etc.].
As to claim 15:
Liang as modified by Leu discloses:
each of the categories of wafer hotspot types comprises a corresponding text description of a proposed layout modification [Paragraph 0121 teaches defect pattern library and frequent failure defect library, including text descriptions; Fig. 9, 1610-1630 teach descriptions of the layouts].
As to claim 16:
Liang as modified by Leu discloses:
output a text description of a proposed layout modification [Paragraph 0097 teaches obtaining the defect text data; Paragraph 0121 teaches defect pattern library and frequent failure defect library, including text descriptions; Fig. 9, 1610-1630 teach descriptions of the layouts].
As to claim 17:
Liang discloses:
the machine learning system comprises a convolutional neural network [Paragraph 0039 teaches the defect classification model is a convolutional neural network model].
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (U.S. Publication No. 2019/0213725) hereinafter Liang, in view of LEU et al. (U.S. Publication No. 2020/0026819) hereinafter Leu, and further in view of AMTHOR et al. (U.S. Publication No. 2023/0111345) hereinafter Amthor.
As to claim 18:
Liang discloses:
An apparatus comprising: a first block configured to designate a previously identified wafer hotspot in an input layout file that comprises a portion of an integrated circuit layout, wherein each input layout file includes a hotspot label that designates the previously identified wafer hotspot [Paragraph 0006 teaches receiving a defect list and a circuit layout image; Paragraph 0007 teaches receiving a defect list and a circuit layout image; Paragraph 0033 teaches circuit layout image is a circuit design chart corresponding to the circuit board under inspection];
a second block configured to convert information from the input layout file to generate an image of the portion of the integrated circuit layout with the previously identified wafer hotspot [Paragraph 0007 teaches generating a first cropped defect image based on defect location according to the circuit layout image, therefore, generating an image of the portion of the integrated circuit layout with the previously identified defect];
match the previously identified wafer hotspot to a corrected portion of the integrated circuit layout [Paragraph 0007 teaches defect classifying module inputs the first cropped defect image to a defect classifying model; Paragraph 0038 teaches input the first cropped defect image to a defect classifying model for classification into a type of defect, therefore, matching the hotspot to one of a plurality of categories; Paragraph 0041 teaches classifier determines to which defect type the defect belongs].
Liang does not appear to expressly disclose wherein the image comprises TIFF, BMP, JPG, JPEG or PNG data; an image-to-image translation predictor.
Leu discloses:
the image comprises TIFF, BMP, JPG, JPEG or PNG data [Paragraph 0031 teaches defect data will be processed to be JPG, TIFF, PNG; Paragraph 0039 teaches the file format of defect image is different with the file format of design layout pattern, i.e., JPEG; Paragraph 0015 teaches defect layout pattern groups file information in the design layout pattern coordinate regions are converted to systematic defect text and image data file].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of the cited references and modify the invention as taught by Liang, by incorporating images comprising TIFF, BMP, JPG, JPEG or PNG data, as taught by Leu [Paragraph 0031, 0039], because both applications are directed to identification and classification of defects in wafers; incorporating images specifically of a certain format, as opposed to a different image format is a simple substitution of one known element for another to obtain predictable results.
Neither Liang nor Leu appear to expressly disclose an image-to-image translation predictor.
Amthor discloses:
an image-to-image translation predictor [Paragraph 0068 teaches image-to-image transformation can then be carried out using a machine-learned algorithm].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of the cited references and modify the invention as taught by Liang, by incorporating an image-to-image translation predictor, as taught by Amthor [Paragraph 0068], because the applications are directed to identification and classification of defects; incorporating an image-to-image translation predictor to perform the clustering or matching of the images is a simple substitution of one known element for another to obtain predictable results.
As to claim 20:
Liang as modified by Leu discloses:
the input layout file comprises a Graphic Design System data file [Paragraph 0096 teaches the design layout pattern format can be GDS format, GDS-II format, etc.].
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (U.S. Publication No. 2019/0213725) hereinafter Liang, in view of LEU et al. (U.S. Publication No. 2020/0026819) hereinafter Leu, and further in view of AMTHOR et al. (U.S. Publication No. 2023/0111345) hereinafter Amthor, and further in view of Kwang et al. (U.S. Publication No. 2009/0268958) hereinafter Kwang.
As to claim 19:
Liang discloses all the limitations as set forth in the rejections of claim 18 above, but does not appear to expressly disclose generate an output image file that depicts a same portion of the integrated circuit layout as the portion depicted in the input layout file, but with proposed changes to eliminate the previously identified wafer hotspot.
Kwang discloses:
generate an output image file that depicts a same portion of the integrated circuit layout as the portion depicted in the input layout file, but with proposed changes to eliminate the previously identified wafer hotspot [Paragraph 0062 teaches if a match is found, retrieve the stored correction guidance descriptions for the matched known hotspot configuration and use this information to correct the received pattern clip].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings of the cited references and modify the invention as taught by Liang, by generating an output image file that depicts a same portion of the integrated circuit layout as the portion depicted in the input layout file, but with proposed changes to eliminate the previously identified wafer hotspot, as taught by Kwang [Paragraph 0062], because the applications are directed to identification and classification of defects in wafers; determining and providing layout modifications improves manufacturability of the designs (See Kwang Para [0041]).
Response to Arguments
The following is in response to arguments filed on May 28, 2026. Arguments have been fully and respectfully considered.
Claim Rejections - 35 USC § 101
Applicant’s arguments in regards to claims 1 to 20 have been carefully and respectfully considered, but are not persuasive.
In regards to claim 1, Applicant argues that “viewed as a whole, the claim is rooted in a specific improvement to computer-based semiconductor design workflows, not in the abstract idea of categorization itself. The matching operation cannot practically be performed in the human mind and is inseparable from the required image generation, machine execution, and data transformation steps”.
In response to the preceding argument, Examiner respectfully disagrees, and respectfully submits that as presently presented, the matching operation can be performed in the human mind, with the aid of pen and paper. The claims recite “apply a machine learning model to the image data to match…”, which as further described in the rejections above, is merely saying “applying it”, since it is recited at a high-level of generality, and amounts to no more than mere instructions to apply the exception using generic computer components, because it does no more than invoking computers or other machinery merely as a tool to perform an existing process.
In regards to claim 1, Applicant further argues that “such use of machine learning to process layout-derived image data and generate layout modification guidance constitutes a practical application”.
In response to the preceding argument, Examiner respectfully disagrees, and respectfully points out that the use of the machine learning as presently presented, is recited at a high level of generality. Adding a “computer-aided” limitation, computer components, or a neural network recited at a high-level of generality without significantly more, to a claim covering an abstract concept, is insufficient to render a claim eligible where the claims are silent as to how the computer aids the method, the extent to which a computer aids the method, or the significance of the computer to the performance of the method, and amounts to merely saying “apply-it”. In order for a machine to add significantly more, it must “play a significant part in permitting the claimed method to be performed, rather than function solely as an obvious mechanism for permitting a solution to be achieved more quickly”. (See, e.g., Versata Development Group v. SAP America, 793 F.3d 1306, 1335, 115 USPQ2d 1681, 1702 (Fed. Cir. 2015); See MPEP 2106.05(f)(II)(v) Requiring the use of software to tailor information and provide it to the user on a generic computer, Intellectual Ventures I LLC v. Capital One Bank (USA), 792 F.3d 1363, 1370-71, 115 USPQ2d 1636, 1642 (Fed. Cir. 2015)).
In regards to claim 1, Applicant further argues that “claim 1 reflects a technological improvement to computerized layout analysis workflows”.
In response to the preceding argument, Examiner respectfully disagrees, and respectfully submits that it is not clear, from the Applicant’s argument, what is the specific improvement in the functioning of a computer, or the improvement to another technology or technical field, that is achieved with the claimed invention. Furthermore, it is also not apparent from the Applicant’s argument, how such improvement correlate with the claim language as presently presented. Therefore, the claims are directed to an abstract idea without significantly more, under the “Mental Processes” grouping of abstract ideas, as further detailed in the rejections above. 101 Rejections are hereby sustained.
Claim Rejections - 35 USC § 103
Applicant’s arguments have been carefully and respectfully considered, but are moot in view of new grounds of rejections, as necessitated by the amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAQUEL PEREZ-ARROYO whose telephone number is (571)272-8969. The examiner can normally be reached Monday - Friday, 8:00am - 5:30pm, Alt Friday, EST.
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/RAQUEL PEREZ-ARROYO/Primary Examiner, Art Unit 2169
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