DETAILED ACTION
This action is responsive to the following communications: the Application filed July 19, 2023, and Response to election / restriction filed December 09, 2025.
Claims 1-20 are pending. Claims 19-20 are withdrawn from consideration as being drawn to non-elected inventions without traverse. Claims 1 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 19, 2023, July 27, 2023, February 12, 2025, March 04, 2025, March 20, 2025, April 14, 2025 and January 21, 2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because:
Figures 1A-2A should be designated by a legend such as –Prior Art—because only that which is old is illustrated. See MPEP 608.02(g).
Applicant’s Figures 1A-2A are prior art as evinced by Figures in US 9,471,486, which was patented October 18, 2016 (more than one year before instant applicant's earliest effective filing date of the claimed invention).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Independent claims 1 and 15, recite “a re-writeable memory cell” and “a multi-time programmable memory cell”. The examiner believes multi-time programmable memory cells include re-writeable memory cells within the semiconductor memory, except for one-time programmable memory cells. Clarification is required.
Claims 2-14 and 15-18 are rejected due to claim dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4, 8-10 and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Petti et al. (US 2020/0273512).
Regarding independent claims 1 and 15, as best as can be understood, Petti et al. disclose an apparatus comprising:
a memory cell (e.g., FIGS. 2-3: 230 MRAM) comprising a reversible resistance-switching memory element (232 MTJ) coupled in series with a selector element (238 SEL), wherein:
the memory cell may be selectively configured as either a re-writeable memory cell (e.g., para. 0052: MRAM element 321 can be optionally erased into an initial state, and then a desired data value can be written or programmed into MRAM element 321) or a multi-time programmable memory cell (MRAM element 321 can be written or programmed without erasing);
the selector element comprises a first switch resistance (e.g., para. 0018: a parallel state) and a second switch resistance (anti-parallel state);
the resistance-switching memory element comprises a first memory element resistance (e.g., para. 0018: a parallel state) and a second memory element resistance (anti-parallel state); and
the memory cell functions as a multi-time programmable memory cell regardless of whether the resistance-switching memory element has the first memory element resistance or the second memory element resistance (see e.g., FIGS. 2-3 and accompanying disclosure, e.g., para. 0052).
Regarding claim 2, which depends from claim 1, Petti et al. disclose the first switch resistance is a resistance of the selector element as fabricated (see e.g., FIG. 9 and accompanying disclosure; further, it’s a well-known technology in the MRAM area).
Regarding claim 4, which depends from claim 1, Petti et al. disclose the memory cell is configured to be programmed a first time by applying one or more pulses comprising a first voltage (e.g., para. 0024: MTJ … written … corresponding electrical pulses …; further, it’s a well-known technology in the MRAM area).
Regarding claims 8-10, which depends from claim 1, Petti et al. disclose the memory cell is configured as a multi-time programmable memory cell that may have a first resistance and a second resistance, wherein the first resistance comprises the first switch resistance and the second resistance comprises the second switch; the second resistance further comprises the first memory element resistance or the second memory element resistance; and the memory cell is configured as a multi-time programmable memory cell that may have a third resistance that comprises the second switch resistance (e.g., para. 0018: a parallel state … anti-parallel state; further, it’s a well-known technology in the MRAM area).
Regarding claim 13, which depends from claim 1, Petti et al. disclose the reversible resistance-switching memory element comprises a magnetic tunnel junction memory element (e.g., FIG. 2 and accompanying disclosure).
Regarding claims 14 and 16, which depends from claims 1 and 15, respectively, Petti et al. disclose the selector element comprises an ovonic threshold switch (para. 0025: ovonic threshold switch).
Regarding claim 17, which depends from claim 15, Petti et al. disclose each selector element comprises a first switch resistance and a second switch resistance; each magnetic tunnel junction memory element is configured to reversibly switch between a first memory element resistance and a second memory element resistance; and each memory cell configured as a multi-time programmable memory cell that functions regardless of whether the magnetic tunnel junction memory element has the first memory element resistance or the second memory element resistance (e.g., FIGS. 2-3 and accompanying disclosure).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5-7, 11-12 and 18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Petti et al. (US 2020/0273512).
Regarding claim 3, Petti et al. teach the limitations of claim 1.
Petti et al. do not explicitly disclose the selector element is configured to irreversibly switch from the first switch resistance to the second switch resistance in response to a forming operation performed on the selector element.
However, irreversibly switch in cross-point memory is a well-known technology for a type of non-volatile memory for its purpose.
For support, of the above asserted facts, see for example, Chang et al. (US 2022/0351774), e.g., para. 0029: …the PCRAM cell … and may irreversibly switch to a HRS …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Chang et al. to the teaching of Petti et al. such that a memory, as taught by Petti et al., utilizes a switch transistor, as taught by Chang et al., for the purpose of performing enhanced programming operations.
Regarding claims 5-7 and 18, Petti et al. teach the limitations of claims 4 and 15, respectively.
Petti et al. do not explicitly disclose the first voltage comprises a forming voltage of the selector element; the memory cell is configured to be programmed a second time by applying one or more pulses comprising a second voltage greater than the first voltage; and the memory cell is configured to be programmed a third time by applying one or more pulses comprising a third voltage greater than the second voltage.
However, applying a forming voltage to a MRAM selector element and applying step voltages to program a MRAM device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply a forming voltage to a memory element because these conventional technology are well established in the art of the memory devices.
Regarding claims 11-12, Petti et al. teach the limitations of claim 8.
Petti et al. do not explicitly disclose the third resistance further comprises a third memory element resistance lower than the first memory element resistance and the second memory element resistance; and the memory cell is configured as a multi-time programmable memory cell that may have a fourth resistance that comprises an open circuit resistance of the resistance-switching memory element and the selector element.
However, forming MRAM by applying different voltages to program a MRAM device is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply a forming voltage to a memory element because these conventional technology are well established in the art of the memory devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825