Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
1. Claims 1-2, 4-5, 7 and 20 are rejected under 35 U.S.C. 102(a1) as being anticipated by Chen et al. (US 2020/0058669; hereinafter Chen).
Regarding claim 1, Chen, in fig. 1, discloses a three-dimensional semiconductor
memory device comprising: a first substrate 202; a peripheral circuit structure 206 on the first
substrate 202; and a cell array structure 242 on the peripheral circuit structure 206, wherein the
cell array structure 242 includes: a second substrate 244; a stack structure 242 between the
second substrate 244 and the peripheral circuit structure 206, the stack structure 242 including a
plurality of interlayer dielectric layers 236 and a plurality of conductive patterns 234 that are
stacked alternately with the plurality of interlayer dielectric layers 236 ([0053]); a plurality of vertical channel structures 228 that include respective portions in the stack structure 242 and
include a plurality of vertical semiconductor patterns 228, respectively ([0054]); and a plurality
of connection vias 251 that include respective portions in the second substrate 244 and are
connected to respective top surfaces of the plurality of vertical semiconductor patterns 228,
wherein the plurality of vertical channel structures 228 include a plurality of first vertical channel structures 228 and a plurality of second vertical channel structures 228, the plurality of first vertical channel structures 228 and the plurality of second vertical channel structures 228 respectively including vertical semiconductor patterns 228 and extending at least partially through the stack structure 242, and wherein the plurality of connection vias 251 overlap the plurality of first vertical channel structures 228, respectively, and do not overlap the plurality of second vertical channel structures 228 (fig. 8).
Regarding claim 2, Chen discloses wherein the plurality of connection vias 251 include a
semiconductor material ([0056]).
Regarding claim 4, Chen discloses wherein the cell array structure 242 includes a cell
array area (the area 242 having channel region 228) and a cell array contact area (staircase area),
the plurality of vertical channel structures 228 include a plurality of first vertical channel
structures 228 on the cell array area and a plurality of second vertical channel structures 228 on
the cell array contact area (fig. 1).
Regarding claim 5, Chen discloses wherein the plurality of vertical channel structures
228 include, respectively, a plurality of buried dielectric patterns 229 that are surrounded by the
plurality of vertical semiconductor patterns 228, respectively, the plurality of vertical
semiconductor patterns 228 include: a plurality of first parts that extend on respective sidewalls
of the plurality of buried dielectric patterns 229; and a plurality of second parts that extend on
respective top surfaces of the plurality of buried dielectric patterns 229, and the plurality of
connection vias 251 are in contact with the plurality of second parts, respectively (fig. 1).
Regarding claim 7, Chen discloses wherein at least one of the plurality of connection vias
include a void or seam therein (fig. 1).
Regarding claim 11, Chen discloses wherein the cell array structure further includes a
common source region in the second substrate, the common source region having a second
conductivity type ([0056]).
Regarding claim 20, Chen, in fig. 1, discloses an electronic system comprising: a three-
dimensional semiconductor memory device that includes a first substrate 202, a peripheral circuit
structure 206 on the first substrate 202, and a cell array structure 242 on the peripheral circuit
structure, the cell array structure 242 including a cell array area (the area 242 having channel
region 228) and a cell array contact area (staircase area); and a controller electrically connected
through an input/output pad to the three-dimensional semiconductor memory device ([0050]), the
controller being configured to control the three-dimensional semiconductor memory device,
wherein the cell array structure 242 includes: a second substrate 244; a stack structure 242
between the second substrate 244 and the peripheral circuit structure 206, the stack structure 242
including a plurality of interlayer dielectric layers 236 and a plurality of conductive patterns 234
that are stacked alternately with the plurality of interlayer dielectric layers 236 ([0053]); a
plurality of vertical channel structures 228 that include respective portions in the stack structure
242 and include, respectively, a plurality of vertical semiconductor patterns 228 ([0054]); and a
plurality of connection vias 251 that include respective portions in the second substrate 244 and
are connected to respective top surfaces of the plurality of vertical semiconductor patterns 228, wherein the plurality of vertical channel structures 228 include a plurality of first vertical channel structures 228 and a plurality of second vertical channel structures 228, the plurality of first vertical channel structures 228 and the plurality of second vertical channel structures 228 respectively including vertical semiconductor patterns 228 and extending at least partially through the stack structure 242, and wherein the plurality of connection vias 251 overlap the plurality of first vertical channel structures 228, respectively, and do not overlap the plurality of second vertical channel structures 228 (fig. 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US
2020/0058669) in view of Zhang et al. (US 12,082,411; hereinafter Zhang).
Regarding claims 13, Chen, in fig. 1, discloses a three-dimensional semiconductor
memory device comprising: a first substrate 202; a peripheral circuit structure 206 on the first
substrate 202; and a cell array structure 242 on the peripheral circuit structure 206, wherein the
cell array structure 242 includes: a second substrate 244; a stack structure 242 between the
second substrate 244 and the peripheral circuit structure 206, the stack structure 242 including a
plurality of interlayer dielectric layers 236 and a plurality of conductive patterns 234 that are
stacked alternately with the plurality of interlayer dielectric layers 236 ([0053]); a plurality of
vertical channel structures 228 that include respective portions in the stack structure 242 and
include a plurality of vertical semiconductor patterns 228; a plurality of connection vias 251 that
include respective portions in the second substrate 244 and are connected to respective top
surfaces of the plurality of vertical semiconductor patterns 228; a plurality of cell contact plugs
258 that are connected to the plurality of conductive patterns 234, respectively; a plurality of bit
lines connected 226 to the plurality of cell contact plugs 258, respectively, wherein the plurality of vertical channel structures 228 include a plurality of first vertical channel structures 228 and a plurality of second vertical channel structures 228, the plurality of first vertical channel structures 228 and the plurality of second vertical channel structures 228 respectively including vertical semiconductor patterns 228 and extending at least partially through the stack structure 242, and wherein the plurality of connection vias 251 overlap the plurality of first vertical channel structures 228, respectively, and do not overlap the plurality of second vertical channel structures 228 (fig. 8).
Chen discloses a semiconductor device as above but fails to disclose common source line
on the second substrate and connected to the source vias.
However, Zhang, fig. 3, discloses a plurality of source vias 332 that include respective
portions in the second substrate 322 (col. 13, lines 36-43); and a common source line 336/210 on
the second substrate 322 and connected to the source vias 332 (col. 13, line 62 through col. 14,
line 3). Therefore, it would have been obvious to a person of ordinary skill in the art before the
effective filing date of the claimed invention to form a common source line as taught by Zhang,
since the source of NAND memory string is electrically connected to the part of peripheral
circuit for controlling/sensing the source of NAND memory string through the source line.
Regarding claim 14, Chen discloses wherein the plurality of connection vias 251 include
a polycrystalline silicon layer having a first conductivity type ([0056]).
Regarding claim 15, Chen discloses wherein the cell array structure 242 includes a cell
array area (the area 242 having channel region 228) and a cell array contact area (staircase area),
the plurality of vertical channel structures 228 include a plurality of first vertical channel
structures 228 on the cell array area and a plurality of second vertical channel structures 228 on
the cell array contact area (fig. 1).
Regarding claim 16, Chen discloses wherein the plurality of vertical channel structures
228 include, respectively, a plurality of buried dielectric patterns 229 that are surrounded by the
plurality of vertical semiconductor patterns 228, respectively, the plurality of vertical semiconductor patterns 228 include: a plurality of first parts that extend on respective sidewalls
of the plurality of buried dielectric patterns 229; and a plurality of second parts that extend on respective top surfaces of the plurality of buried dielectric patterns 229, and the plurality of
connection vias 251 are in contact with the plurality of second parts, respectively (fig. 1).
Regarding claim 17, Chen discloses wherein the plurality of vertical channel structures
228 include, respectively, a plurality of buried dielectric patterns 229 that are surrounded by the
plurality of vertical semiconductor patterns 228, respectively, and the plurality of connection vias
251 contact respective top surfaces of the plurality of buried dielectric patterns 229 and the
respective top surfaces of the plurality of vertical semiconductor patterns 228 (fig. 1).
Regarding claim 18, Chen discloses wherein the cell array structure further includes an
etch stop layer between the second substrate 244 and the stack structure 242 ([0058]).
Regarding claim 19, Chen discloses wherein the etch stop layer includes a metal oxide
layer ([0058]).
3. Claims 3, 6 and 8-10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2020/0058669) in view of Zhang (US 12,082,411).
Regarding claim 3, Chen fails to disclose the connection vias include a polycrystalline silicon layer.
However, Zhang discloses the plurality of connection vias (the channel plug 329) include a polycrystalline silicon layer having a first conductivity type (col. 12, lines 34-43). It would have been obvious to one of ordinary skill in the art to have an anode or a cathode material as taught by Zhang, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 6, Zhang discloses wherein the plurality of vertical channel structures
328 include, respectively, a plurality of buried dielectric patterns (not labeled, buried dielectric patterns are formed below and contact the dielectric 320) that are surrounded by the
plurality of vertical semiconductor patterns 328, respectively, and the plurality of connection vias
contact respective top surfaces of the plurality of buried dielectric patterns and the
respective top surfaces of the plurality of vertical semiconductor patterns 328 (fig. 3).
Regarding claim 8, Zhang discloses wherein the cell array structure further includes an
etch stop layer 320 between the second substrate 322 and the stack structure (fig. 3).
Regarding claim 9, Zhang discloses wherein the etch stop layer includes a metal oxide
layer (fig. 3).
Regarding claim 10, Zhang discloses wherein an interface between one of the plurality of
connection vias and one of the plurality of vertical semiconductor patterns 328 is in the etch
stop layer 320 (fig. 3).
Regarding claim 12, Zhang discloses a plurality of source vias 332 that include respective portions in the second substrate 322 (col. 13, lines 36-43); and a common source line 336/210 on the second substrate 322 and connected to the source vias 332 (fig. 3 & col. 13, line 62 through col. 14, line 3).
Response to Arguments
4. Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Vu whose telephone number is (571) 272-1798. The examiner can normally be reached on Monday-Friday from 8:00am to 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempt to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke H can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/DAVID VU/
Primary Examiner, Art Unit 2818
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