Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 – 15 and 21 – 25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e. an abstract idea) without significantly more.
In regarding claims 1, 8 and 21:
Step 1:
Claims 1, 8 and 21 are directed towards a process, machine, manufacture or composition of matter which is/are statutory subject matter.
Step 2A:
Prong 1:
Claims 1, 8 and 21 are directed an idea for determining a cost of a path through the lattice representation, which is an abstract idea.
Consideration of the claimed elements:
The claim 1 in the instant application include:
A method, comprising:
generating a lattice representation corresponding to an auditory utterance;
traversing the lattice representation based, at least, on log probabilities of emissions for units of the auditory utterance;
determining a final unit of the auditory utterance is emitted;
applying a skip-connection emission from a final unit frame to an end frame of a plurality of frames; and
determining a cost of a path through the lattice representation, wherein the skip- connection emission has a zero-value cost.
The claim 8 in the instant application include:
A system comprising:
at least one processor to:
generate a lattice representation corresponding to an auditory utterance over a plurality of frames;
apply a skip-connection emission from a first frame of the plurality of frames to a selected second frame of the plurality of frames;
traverse the lattice representation based, at least, on log probabilities of emissions for units of the auditory utterance;
determine a final unit of the auditory utterance is emitted; and
determine a cost of a path through the lattice representation, wherein the skip-connection emission has a zero-value cost.
The claim 21 in the instant application include:
A processor comprising:
one or more processing units to determine a cost of a path through a lattice representation traversed using at least one zero-value cost skip-connection emission from a first frame of a plurality of frames to a selected second frame of the plurality of frames.
The steps describe performing mathematical calculations. "Log probabilities," "determining a cost of a path," and "zero-value cost" are mathematical algorithms (e.g., Viterbi decoding or Hidden Markov Model lattice traversals). The claimed limitation can be broadly read as mathematical concepts.
Prong 2:
The claims include additional elements of:
at least one processor.
It is considered as a general computer hardware.
Moreover, the claim limitations that are not indicative of integration into a practical application.
Thus, the above recited additional elements perform no more than their basic computer function. Generic computer-implementation of a method is not a meaningful limitation that alone can amount to significantly more than an abstract idea. Moreover, when viewed as a whole with such additional element considered as an ordered combination, claims modified by adding a generic memory and processor are nothing more than a purely conventional computerized implementation of an idea in the general field of computer processing and do not provide significantly more than an abstract idea.
Accordingly, the claims are directed to an idea of itself, and therefore not patent eligible.
Step 2B:
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception such as improvements to another technology or technical field, or other meaningful limitations beyond generally linking the use of the judicial exception to a particular technological environment.
Moreover, the claim language that may be separate from the abstract idea (i.e., additional elements) include computer hardware. The additional elements (e.g., computer hardware) perform only basic function, which would be common to every additional element (e.g. computer hardware). They are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception.
Thus, the recited generic additional element (e.g., computer hardware) perform no more than their basic computer function. Generic computer-implementation of a method is not a meaningful limitation that alone can amount to significantly more than an abstract idea. Moreover, when viewed as a whole with such additional element considered as an ordered combination, claims modified by adding a generic memory are nothing more than a purely conventional computerized implementation of an idea in the general field of computer processing and do not provide significantly more than an abstract idea.
Consequently, the identified additional elements taken into consideration individually or in combination fails to amount of significantly more than the abstract idea above.
Regarding claims 2 – 7, 9 – 15 and 22 – 25, the rejection is based on the same rationale described for claims 1, 8 and 21, respectively, because the claims include/inherit the same/similar type of problematic limitation(s) as claims 1, 8 and 21, wherein limitations regarding "generating …", “combining …”, “are …”, “populating …”, “adding …”, “applying …”, “traverses …”, “is …”, “includes …”, “fusing …”, and/or “determine …” is/are of sufficient breadth that it would be substantially directed to or reasonably interpreted as a part of the “mental processes” as the abstract idea (similar to claims 1, 8 and 21 as stated above). It is noted that further additional limitation is merely generic/conventional computer component/steps to implement the abstract idea, which is, individually or in combination, not sufficient to amount to significantly more than the judicial exception. Therefore, the claimed invention as a whole is directed to an ineligible subject matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21, 24 and 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meunier (WIPO Patent Application Publication WO 2001/84534)
Regarding claim 21, Meunier discloses a processor (Fig. 1) comprising:
one or more processing units to determine a cost of a path through a lattice representation traversed (page 8, lines 12 – 14, “the alignment algorithm operates to determine the best path back from any point based upon a score for each path considered”) using at least one zero-value cost skip-connection emission from a first frame of a plurality of frames to a selected second frame of the plurality of frames (Fig. 7, page 12 – 14, determine optimal path from a first frame to a selected second frame of the plurality of frames traversed using at least one zero-value cost skip state transition; dwell count for skip state is zero-value).
Regarding claim 24 (depends on claim 21), Meunier discloses the processor wherein zero-value skip-connection emission is applied from a determined final frame of the plurality of frames (Fig. 7, page 12 – 14, final frame 5).
Regarding claim 25 (depends on claim 21), Meunier discloses the processor wherein the lattice representation includes a respective end state for each frame of the plurality of frames (Fig. 7, page 12 – 14, end state 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5 – 10, 12 – 15 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meunier in view of Peyser et al. (US Patent Application Publication 2021/0233512), hereinafter referred as Peyser.
Regarding claim 8, Meunier discloses a system (Fig. 1) comprising:
at least one processor (Fig. 1, processor) to:
generate a lattice representation corresponding to an auditory utterance over a plurality of frames (page 4, lines 19 – 22, “generating a traceback array having a plurality of rows and one or more columns, with each row of the plurality of rows corresponding to one of a plurality of states in which a traceback path terminates, and each column containing one or more dwell counts for states in the traceback path”; also see Fig. 5);
apply a skip-connection emission from a first frame of the plurality of frames to a selected second frame of the plurality of frames (Fig. 7, page 12 – 14, apply optimal path from a first frame to a selected second frame of the plurality of frames traversed using at least one zero-value cost skip state transition; dwell count for skip state is zero-value);
traverse the lattice representation based, at least, on probabilities of emissions for units (page 7 – 8, statistical representation of state) of the auditory utterance (Fig. 7, page 12 – 14);
determine a final unit of the auditory utterance is emitted (Fig. 7, page 12 – 14, determine final unit circled dot in upper-right corner); and
determine a cost of a path through the lattice representation (page 8, lines 12 – 14, “the alignment algorithm operates to determine the best path back from any point based upon a score for each path considered”), wherein the skip- connection emission has a zero-value cost (Fig. 7, page 12 – 14, optimal path from a first frame to final unit traversed using at least one zero-value cost skip state transition; dwell count for skip state is zero-value).
However, Meunier fails to explicitly disclose wherein the probabilities are log probabilities.
However, in a similar field of endeavor Peyser discloses a speech recognition processing system (abstract). In addition, Peyser discloses the probabilities used for processing frames are log probabilities ([0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Meunier, and use log probabilities for processing. The motivation for doing this is to take an advantage of preventing computer underflow errors with tiny numbers.
Regarding claim 9 (depends on claim 8), Meunier discloses the system wherein the system comprises at least one of:
a system for performing simulation operations;
a system for performing simulation operations to test or validate autonomous machine applications;
a system for performing digital twin operations;
a system for performing light transport simulation;
a system for rendering graphical output;
a system for performing deep learning operations;
a system implemented using an edge device;
a system for generating or presenting virtual reality (VR) content;
a system for generating or presenting augmented reality (AR) content;
a system for generating or presenting mixed reality (MR) content;
a system incorporating one or more Virtual Machines (VMs);
a system for performing operations for a conversational Al application (page 8, HMM for speech processing);
a system for performing operations for a generative Al application;
a system for performing operations using a language model;
a system implemented at least partially in a data center;
a system for performing hardware testing using simulation;
a system for synthetic data generation;
a collaborative content creation platform for 3D assets; or
a system implemented at least partially using cloud computing resources.
Regarding claim 10 (depends on claim 8), Peyser discloses the system wherein the lattice representation is associated with a recurrent neural network transducer (RNN-T) ([0036]).
Regarding claim 12 (depends on claim 8), Meunier discloses the system wherein the at least one processor is further to: apply the skip-connection emission from the final unit to a near-last frame (Fig. 7, last two scenarios).
Regarding claim 13 (depends on claim 12), Meunier discloses the system wherein the near-last frame is an immediately preceding frame of final output frame (Fig. 7, last two scenarios).
Regarding claim 14 (depends on claim 12), Meunier discloses the system wherein the at least one processor is further to: apply a blank emission after the near-last frame; and add a blank cost, for the blank emission, to the cost (Fig. 7, page 12 – 14, optimal path from a first frame to final unit traversed using at least one zero-value cost skip state transition; dwell count for skip state is zero-value).
Regarding claim 15 (depends on claim 8), Meunier discloses the system wherein the lattice representation includes a respective end state for each frame of the plurality of frames (page 13 – 14).
Regarding claim 1, it is corresponding to claim 8, thus, it is interpreted and rejected for the same reason set forth for claim 8.
Regarding claim 2 (depends on claim 1), Meunier discloses the method further comprising: generating a unit schema for the lattice representation; generating a time schema for the lattice representation; and combining the unit schema and the lattice representation (Fig. 5, combine time axis to the lattice representation).
Regarding claim 5 (depends on claim 1), Meunier discloses the method further comprising: adding a blank emission to the path; and adding an associated blank cost to the cost (Fig. 7, page 13 – 14).
Regarding claim 6 (depends on claim 1), Meunier discloses the method further comprising: applying the skip-connection emission from a start frame to an intermediate frame between the start frame and the end frame (Fig. 7, page 12 – 14).
Regarding claim 7 (depends on claim 1), Meunier discloses the method wherein the skip-connection emission traverses a time axis of the lattice representation for two or more frames (Fig. 5).
Regarding claim 22 (depends on claim 21), Meunier fails to explicitly disclose the processor wherein the lattice representation is associated with a recurrent neural network transducer (RNN-T).
However, in a similar field of endeavor Peyser discloses a speech recognition processing system (abstract). In addition, Peyser discloses the lattice representation is associated with a recurrent neural network transducer (RNN-T) ([0036]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Meunier, and the lattice representation is associated with a recurrent neural network transducer (RNN-T). The motivation for doing this is that the process can be more powerful.
Claim(s) 3, 4, 11 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meunier in view of Peyser, and in further view of Bagby et al. (“EFFICIENT IMPLEMENTATION OF RECURRENT NEURAL NETWORK TRANSDUCER IN TENSORFLOW”, 2018 IEEE Spoken Language Technology Workshop (SLT)), hereinafter referred as Bagby.
Regarding claim 3 (depends on claim 2), Meunier fails to explicitly disclose the method wherein one or more labels of at least one of the unit schema or the time schema are omitted.
However, in a similar field of endeavor Bagby discloses a system to perform automatic speech recognition (abstract). In addition, Bagby discloses the system wherein one or more labels of at least one of the unit schema or the time schema are omitted (page 507, col. 1, a blank label ('_')).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Meunier, and one or more labels of at least one of the unit schema or the time schema are omitted. The motivation for doing this is that the fast path can be well defined.
Regarding claim 4 (depends on claim 3), Bagby discloses the method further comprising: populating the one or more labels omitted from the at least one of the unit schema or the time schema (page 507, col. 1, non-blank labels (denoted as 'w*’)).
Regarding claim 11 (depends on claim 8), Meunier fails to explicitly disclose the system wherein the determining the cost of the path further causes the at least one processor to: determine forward weights for a path from a start to an end; determine backward weights for the path; and determine a path cost based at least on one or more loss functions.
However, in a similar field of endeavor Bagby discloses a system to perform automatic speech recognition (abstract). In addition, Bagby discloses the system determine forward weights for a path from a start to an end; determine backward weights for the path; and determine a path cost based at least on one or more loss functions (page 507, col. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Meunier, and determine forward weights for a path from a start to an end; determine backward weights for the path; and determine a path cost based at least on one or more loss functions. The motivation for doing this is that the process can be more powerful.
Regarding claim 23, it is corresponding to claim 11, thus, it is interpreted and rejected for the same reason set forth for claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to QIAN YANG whose telephone number is (571)270-7239. The examiner can normally be reached on Monday-Thursday 8am-6pm.
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/QIAN YANG/
Primary Examiner, Art Unit 2677
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