DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Applicant’s election without traverse of Group I claims 1-13 drawn to a memory device, in the reply filed on 11/26/2025 is acknowledged. Claims 14-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, drawn to method forming a memory device
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 11-12 are rejected under 35 U.S.C. 102 (1) (a) as being anticipated by Rabkin et al (US20220208748A1).
Re claim 1 Rabkin teaches a memory device comprising a memory die wherein the memory die (fig 30A) [0237] comprises:
an alternating stack of insulating layers (32, fig 30A) [0062] and electrically conductive layers (46, fig 30A) [0107] that overlies a backside dielectric material layer (230, fig 30A) [0156];
a memory opening (49, fig 30A) [0096] vertically extending through the alternating stack (32/46, fig 30A) [0062, 0107];
a memory opening fill structure (58, fig 30A) [0096] located in the memory opening (49, fig 30A) [0096] and comprising a vertical stack of memory elements fig 29G) [0262] and a vertical semiconductor channel (60L, fig 29G) [0261];
memory-side metal interconnect structures (98/94/96/168/178 fig 30A) [0117] embedded within memory-side dielectric material layers (160, 90, fig 30A A) [ 0117] that overlie the alternating stack (32, 46, fig 30A) [0096]; and
a conductive via structure (8P/194, fig 30A) [0117] vertically extending between one of the memory-side metal interconnect structures (168, fig 30A) and the backside dielectric material layer (210, fig 30A) [0248]
wherein an entirety of an end surface of the conductive via structure (end of 8p/194, fig 30A) is in contact with the backside dielectric material layer (210, fig 30A).
Re claim 2 Rabkin teaches, the memory device of Claim 1, further comprising a source layer (261, fig 30 A) [0248] underlying the alternating stack (32/46), overlying a portion of the backside dielectric material layer (210, fig 30A) [0248], and contacting a bottom end of the vertical semiconductor channel (60L, fig 30A) [0083].
Re claim 3 Rabkin teaches, the memory device of Claim 2, wherein:
the backside dielectric material layer (210, fig 30A) [0248] has a contoured bottom surface (32C) [0290] such that a bottom surface of a first portion (left side portion of 261, fig 30A) [0248] of the backside dielectric material layer (210, fig 30A) that underlies the memory opening fill structure (58 , fig 30A) [0095] is recessed below (210, FIG 32C-32D) [0292] a horizontal plane including a bottom surface of a second portion (261 below 84, fig 30A) of the backside dielectric material layer (210, fig 30A) that underlies the conductive via structure (8p/194, fig 30A) [0143]; and
the second portion of the backside dielectric material layer (261 below 84, fig 30A) [0248] has a same thickness as the first portion (261 below 58, fig 30A) of the backside dielectric material layer (210, fig 30A) [0290].
Re claim 4 Rabkin teaches the memory device of Claim 1, wherein the conductive via structure (8p/194, fig 30A) [0143] vertically extends at least from a first horizontal plane including a top surface of a bottommost insulating layer (210, fig 30A) [0248] within the alternating stack (32/46) [0107] to a second horizontal plane (top plane of top 32, fig 30A) [0061] including a top surface of a topmost insulating layer (top of 210 ) within the alternating stack (fig 30A) [0270].
Re claim 5 Rabkin teaches, the memory device of Claim 4, wherein the conductive via structure (84, fig 30A) [0143] is not direct contact with any conductive material or with any semiconductor material located below the first horizontal plane (horizontal plane of 210, fig 30A).
Re claim 6 Rabkin teaches, the memory device of Claim 1, wherein:
the memory opening fill structure (58, fig 30A) [0095] further comprises a drain region (63, fig 5F) [0094] contacting a top end of the vertical semiconductor channel (60L, fig 0089];
the memory-side metal interconnect structures (168/98/94/96, fig 30A) [0117] comprise a bit line (98, fig 30A) [0116] that is electrically connected to the drain region (60L, fig 30) through at least one metal via structure (88, fig 30A) [0114]; and
the conductive via structure (8p, fig 30) is electrically connected to the bit line (98/96, fig 30A) through at least one additional metal via structure (194, fig 30A) [114].
Re claim 7 Rabkin teaches, the memory device of Claim 1, further comprising: memory-side bonding pads (178, fig 30A) embedded within the memory-side dielectric material layers (140, fig 30 A) and electrically connected to the memory-side metal interconnect structures(168, fig30A) [0117]; and
a logic die (700, fig 30A) [0118] comprising a peripheral circuit (700, fig 30A) [0118], logic-side metal interconnect structures (780, fig 30A) [0120] embedded in logic-side dielectric material layers [760, fig 30A) [0120] and electrically connected to the peripheral circuit (710, fig 30A) [0118], and logic-side bonding pads (788, fig 30 A) [0120] electrically connected to the logic-side metal interconnect structures (780, fig 30A) [012] and bonded to the memory-side bonding pads (788, fig 30A) [0120].
Re claim 12 Rapkin the memory device of Claim 1, further comprising a dielectric material portion (65, fig 30A) [0075] located adjacent to the alternating stack (32/46, fig 30A) and having a same vertical extent (top to bottom) as that alternating stack (32/46, fig 30A) [0107],
wherein the conductive via structure (8p, fig 30A) [0113] vertically extends through, and is in contact with (8p, fig 30A) [0113] is in contact with, the dielectric material portion (65, fig 30A) [0075].
Re claim 13 Rabkin teaches, the memory device of Claim 1, wherein:
the memory-side metal interconnect structures (168/98/96/94, fig 30A) comprise a plurality of bit lines (98/96/94, fig 30A) that are laterally spaced ( 98/96/94 are laterally spaced, fig 30A) from each other along a first horizontal direction (left to right) and laterally extend along a second horizontal direction (top to bottom, fig 30);
the memory-side metal interconnect structures (168/98/96/94, fig 30A) [0270] further comprise a plurality of dummy bit lines (left and right 94 of 8p, fig 30A, [0116] (electrically isolated from each other) [0116] that are laterally spaced from each other along the first horizontal direction and laterally spaced from the plurality of bit lines along the second horizontal direction by a dielectric filled gap (90, fig 30A) [0115]; and
the conductive via structure (8p, fig 30A) is electrically connected to the plurality of dummy bit lines (right 94, fig 30A) and is electrically isolated from each of the plurality of bit lines (8p is isolated from 98, fig 30A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al (US 20220208748A1) in view of Baraskar et al (US 202110408032A1).
Re claim 8 Rabkin teaches, the memory device of Claim 1,
Rabkin does not teach the conductive via structure vertically extends through and is laterally surrounded by each electrically conductive layer within the alternating stack.
Baraskar teaches, the conductive via structure (76, fig 15A) [0153] vertically extends through and is laterally surrounded by each electrically conductive layer (46, fig 15A) within the alternating stack (32/46, fig 15A) [0142].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Baraskar into the structure of Rabkin to include the conductive via structure vertically extends through and is laterally surrounded by each electrically conductive layer within the alternating stack as claimed.
The ordinary artisan would have been motivated to modify Baraskar in the above manner for the purpose of improve electrical performance.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al (US 20220208748A1) modified by Baraskar et al (US 202110408032A1) as applied to claim 8and further in view of Otsu et al (US 20200343258A1).
Re claim 9 Rabkin in view of Baraskar teach the memory device of claim 8 ,
the memory device (15A) [0142] comprises a vertical stack of cylindrical dielectric semiconductor oxide portions (44, fig 12) [Baraskar 0141] that laterally surrounds the conductive via (76, fig 15) structure and contacts the electrically conductive layers (46A/46B, fig 15) [Barasakar 0141].
Rabkin and Baraskar do not teach the conductive via structure comprises a doped semiconductor material.
Otsu teaches the conductive via structure (76, fig 25) [0124] comprises a doped semiconductor material [0124].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Otsu into the structure of Rabkin and Baraskar to include teach the conductive via structure comprises a doped semiconductor material as claimed.
The ordinary artisan would have been motivated to modify Rabkin and Baraskar based on the teaching of Otsu in the above manner for the purpose of to reducing parasitic capacitance.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin in view of Otsu et al (US 20200343258A1).
Re claim 10 Rabkin does not teach the memory device of Claim 1,
Rabkin does not teach a vertical stack of dielectric material plates and interlaced with the insulating layers within the alternating stack along a vertical direction ,
wherein each dielectric material plate within the vertical stack of dielectric material plates is located at a level of, and is contact with, a respective electrically conductive layer of the electrically conductive layers, and the conductive via structure vertically extends through the vertical stack of dielectric material plates and each insulating layer within the alternating stack.
Otsu teaches a vertical stack of dielectric material plates (74, fig 25) [0121] and interlaced with the insulating layers (232, fig 25) [0077] within the alternating stack (232/2426, fig 25) [0077] along a vertical direction (top to bottom, fig 25).
wherein each dielectric material plate (74, fig 25) within the vertical stack of dielectric material plates (74, fig 25) is located at a level of, and is contact with, a respective electrically conductive layer (246, fig 25) [0122] of the electrically conductive layers (246, fig 25), and the conductive via structure (76, fig 25) [0124] vertically extends through the vertical stack of dielectric material plates (74, fig 25) and each insulating layer (232, fig 25) within the alternating stack (232/246, fig 25) [0122].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Otsu into the structure of Rabkin to include a vertical stack of dielectric material plates and interlaced with the insulating layers within the alternating stack along a vertical direction ,
wherein each dielectric material plate within the vertical stack of dielectric material plates is located at a level of, and is contact with, a respective electrically conductive layer of the electrically conductive layers, and the conductive via structure vertically extends through the vertical stack of dielectric material plates and each insulating layer within the alternating stack as claimed.
The ordinary artisan would have been motivated to modify Rabkin based on the teaching of Otsu in the above manner for the purpose of reducing parasitic capacitance.
Re claim 11 Rabkin in view of Otsu teach the memory device of Claim 10, wherein the conductive via structure (76, fig 25) [Rabkin, 0124] comprises a metallic material [Rabkin, 0124] and is in contact with the vertical stack of dielectric material plates (74, fig 25) and each insulating layer (232, fig 25) [Rabkin, 0077] within the alternating stack (232/246, fig 25) [Rabkin, 0077].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/3/26