Prosecution Insights
Last updated: May 29, 2026
Application No. 18/355,966

SEMICONDUCTOR PACKAGING WITH TRANSPARENCY AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §102
Filed
Jul 20, 2023
Priority
Jul 27, 2022 — provisional 63/392,667
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 838 resolved
+16.6% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
14 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
46.9%
+6.9% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§102
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of claims 1-12 in the reply filed on 2/9/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-8 and 21-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abe US 4,763,407. Regarding claim 1, Abe shows a device, comprising: a substrate ( element 10 in FIG. 2C) including: a base portion with a first surface (top surface of element 10) and a second surface (bottom surface of element 10) opposite to the first surface; a plurality of walls ( frame 14) protruding from the first surface of the base portion (element 10), each one of the plurality of walls including an end surface that faces away from the base portion (see FIG. 2A-2C); and a cavity ( portion between frame 14) between the plurality of walls; a first die (die 11) within the cavity and on the first surface of the base portion (see FIG. 2B); and a silicone-based transparent resin ( resin 17 and col. 1) within the cavity, the silicone-based transparent resin encasing the first die (see FIG. 2C). Regarding claim 2, Abe shows a device, comprising, wherein the end surfaces of the plurality of walls (frame 14) are bare (as shown in FIG. 2C). Regarding claim 3, Abe shows a device, comprising, wherein the silicone-based transparent resin (resin 17) includes a surface that is transverse to the plurality of walls (frame 14), and the surface of the silicone-based transparent resin (resin 17) extends between opposite ones of the plurality of walls (frame 14). Regarding claim 4, Abe shows a device, comprising, wherein: the silicone-based transparent resin (resin 17) further includes a first thickness that extends from the first surface of the base portion to the surface of the silicone-based transparent resin (thickness between top surface of element 10 and step portion of frame 14); and the plurality of walls have a second thickness that extends from the end surfaces of the first surface of the base portion to the plurality of end surfaces of the walls, the second thickness being greater than the first thickness (see FIG. 2C). Regarding claim 5, Abe shows a device, comprising, wherein the surface of the silicone-based transparent resin (resin 17) is in closer proximity to the first surface of the base substrate relative to the plurality of end surfaces of the plurality of walls (frame 14). Regarding claim 6, Abe shows a device, further comprising a first wire bond ( wire 13) having a first end coupled to the first die and a second end opposite the first end coupled to the base portion of the substrate (see FIG. 2C). Regarding claim 7, Abe shows a device, comprising, wherein the silicone-based transparent resin (resin 17) covers the end surfaces of the plurality of walls (frame 14). Regarding claim 8, Abe shows a device, comprising, wherein the silicone-based transparent resin (Resin 17) includes: a first portion in the cavity having a first thickness; and a second portion on the first portion and on the end surfaces of the plurality of walls, the second portion having a second thickness less than the first thickness (see FIG. 2C). Regarding claim 21, Abe shows a device, comprising a base portion (element 10) with a first surface and a second surface opposite to the first surface ( top and bottom surface of element 10) ; a plurality of walls (frame 14) on the first surface, the plurality of walls protrude outward from the first surface, and each respective wall of the plurality of walls has an end surface that faces away from the base portion (see FIG. 2C); a recess (space between frame 14) defined by a first surface of the base portion and the plurality of walls (frame 14), and the recess is surrounded by the plurality of walls (frame 14); one or more die within the recess and on the first surface of the base portion; a silicon-based transparent resin (resin 17) within the recess, the silicon transparent resin encasing the one or more die (die 11), the silicon-based transparent resin includes an exposed surface that faces away from the base portion and overlaps the one or more die, and the silicon-based transparent resin covers the end surfaces of the plurality of walls (frame 14 and see FIG. 2A-2C). Regarding claim 22, Abe shows a device, further comprising a wire (wire 13) within the recess and coupled to a respective die of the one or more die, and the wire is encased within the silicon- based transparent resin (resin 17). Regarding claim 23, Abe shows a device, further comprising, wherein the exposed surface of the silicon-based transparent resin (resin 17) is further from the base portion that the end surfaces of the plurality of walls (frame 14). Regarding claim 23, Abe shows a device, further comprising wherein the plurality of walls are along singulation lines (see FIG. 5-9 with respect to FIG. 2C). Regarding claim 25, Abe shows a device, comprising a base (element 10) portion with a first surface and a second surface opposite to the first surface; a plurality of walls (frame 14) on the first surface, the plurality of walls protrude outward from the first surface, and each respective wall of the plurality of walls has an end surface that faces away from the base portion; a recess defined by a first surface of the base portion and the plurality of walls, and the recess is surrounded by the plurality of walls; one or more die within the recess and on the first surface of the base portion; a silicon-based transparent resin within the recess, the silicon transparent resin (resin 17) encasing the one or more die (die 11), the silicon-based transparent resin includes an exposed surface that faces away from the base portion and overlaps the one or more die, and the exposed surface is recessed relative to the end surfaces of the plurality of walls (frame 14). Regarding claim 26, Abe shows a device, further comprising a wire within the recess and coupled to a respective die (die 11) of the one or more die, and the wire (wire 13) is encased within the silicon- based transparent resin (resin 17). Regarding claim 27, Abe shows a device, further comprising, wherein the end surfaces of the plurality of walls are further from the base portion than the exposed surface of the silicon-based transparent resin (resin 17). Regarding claim 28, Abe shows a device, further comprising, wherein the plurality of walls (frame 14) are along singulation lines (see FIG. 5-9 with respect to FIG. 2c). Allowable Subject Matter Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jul 20, 2023
Application Filed
Feb 27, 2026
Non-Final Rejection mailed — §102
Apr 30, 2026
Applicant Interview (Telephonic)
Apr 30, 2026
Examiner Interview Summary
May 14, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642152
POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE ARRANGEMENT
3y 0m to grant Granted May 26, 2026
Patent 12642145
SEMICONDUCTOR PACKAGE
2y 8m to grant Granted May 26, 2026
Patent 12642124
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
2y 9m to grant Granted May 26, 2026
Patent 12635580
SEMICONDUCTOR PACKAGES
3y 1m to grant Granted May 19, 2026
Patent 12635551
CHIP PACKAGE STRUCTURE
2y 9m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+8.0%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allowance rate.

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