DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on December 10, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 20, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Method of Manufacturing Memory Device With Backside Source Layer
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-13) in the reply filed on November 7, 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines: 12-13 recite the limitation “forming an upper insulating layer to cover the portion of an exposed channel layer and the gate stack structure…” it is unclear if the portion of an exposed channel layer refers to the previously defined exposed portion of the channel layer in line 11 or if it is supposed to be a newly defined portion of an exposed channel. For purposes of examination his will be interpreted as “forming an upper insulating layer to cover the portion of the channel layer exposed and the gate stack structure…”
Claim 1, lines: 14-16 recite the limitation “removing a portion of the upper insulating layer to expose a portion of the channel layer; and forming a source layer covering the portion of the exposed channel layer and the upper insulating layer.” It is unclear if the portion of the exposed channel layer refers to the portion defined in line 14 of the portion defined in claim 11. For purposes of examination his will be interpreted as “removing a portion of the upper insulating layer to expose another portion of the channel layer; and forming a source layer covering the another portion of the
Claim 7, lines: 10-13 recite the limitation “removing a portion of the memory layer and at least a portion of the substrate to expose a portion of the channel layer; forming an upper insulating layer to cover a portion of an exposed channel layer and the gate stack structure”, it is unclear if a portion of an exposed channel layer refers to the previously defined portion of the channel layer or if it is a new portion of another exposed channel layer. For purposes of examination this will be interpreted as “removing a portion of the memory layer and at least a portion of the substrate to expose a portion of the channel layer; forming an upper insulating layer to cover the portion of the channel layer exposed and the gate stack structure”. Claim 7, lines: 14-17 recite the limitation “removing a portion of the upper insulating layer to expose the portion of the channel layer; and forming a source layer covering the portion of the exposed channel layer and the upper insulating layer.” It is unclear if the portion of the channel layer refers to the portion exposed in line 11 or is another portion, it is also unclear whether the portion of the exposed channel layer refers to the old reference in claim 12 or another new portion. For purposes of examination this will be interpreted as “removing a portion of the upper insulating layer to expose the portion of the channel layer exposed; and forming a source layer covering the portion of the channel layer exposed and the upper insulating layer.”
Allowable Subject Matter
Claims 1-13 would be allowed if rewritten to overcome the 112 rejections above.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Zhang (US 2021/0375828), Zhang (US Pat. No. 11,158,622), Kanamori (US 2021/0296358), Hwang (US 2018/0358372), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 1 (from which claims 2-6 depend), removing the substrate to expose the memory layer; removing a portion of the memory layer to expose a portion of the channel layer; forming an upper insulating layer to cover the portion of an channel layer exposed and the gate stack structure…
Regarding Claim 7 (from which claims 8-13 depend), removing a portion of the memory layer and at least a portion of the substrate to expose a portion of the channel layer; forming an upper insulating layer to cover the portion of the channel layer exposed and the gate stack structure…
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang (US 2021/0375828) discloses (Figs. 3A-3P) a sacrificial stack 308 in substrate 302, memory layers 315/316/317 on channel 318, replacing gates in Fig. 3E, removing substrate 302, forming conductive layers 359 in removed opening. Zhang does not disclose “forming an upper insulating layer to cover the portion of an channel layer exposed and the gate stack structure…”
Zhang (US Pat. No. 11,158,622) discloses (Figs. 3A-3P) a sacrificial stack 308 in substrate 302, memory layers 315/316/317 on channel 318, replacing gates in Fig. 3E, removing substrate 302, forming conductive layers 359 in removed opening. Zhang does not disclose “forming an upper insulating layer to cover the portion of an channel layer exposed and the gate stack structure…”
Kanamori (US 2021/0296358) discloses (Figs. 15-30) a stack MS1 on a substrate 10 where word lines WLs replace sacrificial layers 310/312, memory layer 132 on channel 130, removing the substrate 10 in Fig. 29, and forming input/output pad 195 on exposed regions. Kanamori does not disclose “forming an upper insulating layer to cover the portion of an channel layer exposed and the gate stack structure…”
Hwang (US 2018/0358372) discloses (Figs. 8-13) a method of forming sacrificial layer 125 and insulating layer 120 stack on substrate LS, a memory layer CP on channel CH, replacing 125 to form gate GP, flipping and removing the substate LS in Fig. 12, forming a conductive layer 10 over the removed LS area. Hwang does not disclose “forming an upper insulating layer to cover the portion of an channel layer exposed and the gate stack structure…”
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/G.G.R/Examiner, Art Unit 2812
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