DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 11-12 in the reply filed on 01/14/2026 is acknowledged.
Claims 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/14/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10, 13-16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Carta et. al, U.S. Pat. Pub. 2006/0214242, hereafter Carta, in view of Okumura et. al., U.S. Pat. 6,060,747, hereafter Okumura (of record), and further in view of Chang et. al., U.S. Pat. 8,431,457, hereafter Chang.
Regarding claim 1, Carta discloses (Figs 1A, 1B) a semiconductor device [100] comprising:
a semiconductor substrate [102] which has an upper surface (top surface of SiC body) and a lower surface (bottom surface facing drain contact metal [106]), has a drift (par. [0022]) region [105] of a first conductivity type (N-type, par. [0022]) between the upper surface and the lower surface, and contains silicon carbide (par. [0021], Fig. 1B);
a plurality of first gate trench portions [112] (par. [0023]) which are provided from the upper surface of the semiconductor substrate [102] to an inside of the semiconductor substrate (see Fig. 1B) and arranged side by side on the upper surface of the semiconductor substrate in a first direction (horizontal direction in Figs 1A, 1B);
a first mesa portion [116] which is sandwiched between two of the first gate trench portions [112] in the first direction (horizontal direction);
a source region [118] of the first conductivity type (N-type) which is provided in the first mesa portion [116], is arranged between the upper surface of the semiconductor substrate [102] and the drift region [105], and has a doping concentration higher than that of the drift region (par. [0022]-[0023]);
Carta fails to explicitly disclose further comprising:
an interlayer dielectric film which is provided above the upper surface of the semiconductor substrate;
an upper-surface electrode which is provided above the interlayer dielectric film;
a mesa facing region which is not sandwiched between two of the first gate trench portions in the first direction and is arranged to face the first mesa portion in a second direction different from the first direction;
an interlayer dielectric film which is provided above the upper surface of the semiconductor substrate;
an upper-surface electrode which is provided above the interlayer dielectric film; and
a contact hole which is provided in the interlayer dielectric film in the mesa facing region and connects the upper-surface electrode and the upper surface of the semiconductor substrate, wherein the contact hole is not provided in the interlayer dielectric film above the first mesa portion, and the source region is provided to extend from the first mesa portion to the mesa facing region and is connected to the upper-surface electrode via the contact hole.
PNG
media_image1.png
730
579
media_image1.png
Greyscale
However, Okumura discloses (Figs 5,7) further comprising:
a mesa facing region (see annotated Fig. 7) which is not sandwiched between two of the first gate trench portions [16] in the first direction and is arranged to face the first mesa portion in a second direction different from the first direction (see annotated Fig. 7 above);
an interlayer dielectric film [17] which is provided above the upper surface of the semiconductor substrate [12],[11],[19p] (see Fig. 5);
an upper-surface electrode [18] which is provided above the interlayer dielectric film [17]; and
a contact hole (space interlayer dielectric portions [17] where the source electrode [18] contacts the substrate [12]) which is provided in the interlayer dielectric film [17] in the mesa facing region and connects the upper-surface electrode [18] and the upper surface of the semiconductor substrate [12] , wherein the contact hole is not provided in the interlayer dielectric film above the first mesa portion, and the source region [13] is provided to extend from the first mesa portion to the mesa facing region and is connected to the upper-surface electrode [18] via the contact hole.
Similarly, Chang teaches (see annotated Fig. 1D) a mesa facing region that connects mesas between gate trenches [104].
PNG
media_image2.png
652
396
media_image2.png
Greyscale
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang, because Chang teaches (Col. 4, lines 12-28) that relocating source contact hole away from the active region improves breakdown voltage characteristics of a power semiconductor device.
Regarding claim 2, Carta in view of Okumura in view of Chang discloses everything as applied above. Okumura further discloses (see annotated Fig. 7 above) comprising a plurality of first mesa portions including the first mesa portion, wherein the source regions [13] of the plurality of the first mesa portions are connected to each other in the mesa facing region. It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 3, Carta in view of Okumura in view of Chang discloses everything as applied above. Chang further discloses (Fig. 1D) wherein the contact hole [109] is arranged to face the plurality of the first mesa portions [106] in the second (vertical) direction. It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 4, Carta in view of Okumura in view of Chang discloses everything as applied above. Chang further discloses (Fig. 1D) wherein the contact hole [109] has a longer side in the first (horizontal) direction. It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 5, Carta in view of Okumura in view of Chang discloses everything as applied above. Okumura further discloses (Fig. 5) further comprising a base region [12] of a second conductivity type (p-type) which is provided in the first mesa portion and arranged between the source region [13] and the drift region [11], wherein the base region [12] is provided to extend from the first mesa portion to the mesa facing region (the base region is below the source contact region [13] in Fig. 7, see Fig. 5) , and is connected to the upper-surface electrode [18] via the contact hole (between ILD portions [17] in Fig. 5). It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 6, Carta in view of Okumura in view of Chang discloses everything as applied above. Chang further discloses (Fig. 32AA’) wherein the base region [3248] is not exposed to the upper surface of the semiconductor substrate in the first mesa portion (upper surface of the source region [3232]). It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 7, Carta in view of Okumura in view of Chang discloses everything as applied above. Carta further discloses (Fig. 1A) wherein each of the first gate trench portions has a longer side in the second direction (vertically). It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 8, Carta in view of Okumura in view of Chang discloses everything as applied above. Okumura further discloses a micrometer size trench (Col. 6, line 38), but fails to explicitly disclose wherein a length of each of the first gate trench portions in the second direction is 3 μm or more and 20 μm or less.
However, this range is obvious over the combination of references because the gate trench length is a result effective variable controlling breakdown voltage characteristics of the power MOSFET. A routine optimization of this parameter thus would be obvious to one of ordinary skill in the art prior to effective filing date of the instant application. The recited range is also close to the size of the trench in Okumura, although width of the trench rather than length was cited in this prior art reference (See MPEP, 2144.05.I and IIA).
Regarding claim 9, Carta in view of Okumura in view of Chang discloses everything as applied above. All 3 references disclose “wherein a distance between two of the first gate trench portions adjacent to each other in the first direction is shorter than a length of the first gate trench portion in the second direction” (Carta, Fig. 1A, Okumura, Fig. 7, Chang, Fig. 1D).
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 10, Carta in view of Okumura in view of Chang discloses everything as applied above. Carta further discloses (Fig. 1B) wherein the plurality of first gate trench portions [112] are separated from each other.
Regarding claim 13, Carta in view of Okumura in view of Chang discloses everything as applied above. Chang further discloses (Fig. 1D) further comprising a plurality of second gate trench portions [104] which are provided from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, arranged side by side on the upper surface of the semiconductor substrate in the first direction (horizontally), and arranged to face the plurality of first gate trench portions in the second direction (vertically, wherein the mesa facing region is arranged between the plurality of first gate trench portions and the plurality of second gate trench portions (these are top and bottom trenches [104] from the Mesa facing region annotated above).
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 14, Carta in view of Okumura in view of Chang discloses everything as applied above.
The limitations “further comprising a second mesa portion which is sandwiched between two of the second gate trench portions in the first direction, wherein the second mesa portion has the source region, the contact hole is not provided in the interlayer dielectric film in the second mesa portion, and the source region of the second mesa portion is provided to extend from the second mesa portion to the mesa facing region, and is connected to the upper-surface electrode via the contact hole” is obvious over the combination of references because it merely corresponds to a virtually identical structures above and below the mesa facing region of Fig. 1D of Chang.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Regarding claim 15, Carta in view of Okumura in view of Chang discloses everything as applied above.
Chang further discloses (Fig. 1D) wherein a distance between two of the first gate trench portions [104] adjacent to each other in the first direction (horizontally) is shorter than a distance between the plurality of first gate trench portions [104] and the plurality of second gate trench portions [104] (above and below the mesa facing region indicated above) in the second direction (vertically, see Fig. 1D or annotated Fig. 1D above).
Regarding claim 16, Carta in view of Okumura in view of Chang discloses everything as applied above. Carta in view of Okumura in view of Chang fails to explicitly disclose wherein a distance between the plurality of first gate trench portions and the plurality of second gate trench portions in the second direction is 2 μm or less.
However, it would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify the distance between first and second gate trenches to meet this limitation because it was held that a change in size is within the ability of one of ordinary skill in the art.
In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.).
In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
(MPEP, latest edition, 2144.04.IV.A)
Regarding claims 19 and 20, Carta in view of Okumura in view of Chang discloses everything as applied above.
“further comprising a plurality of second gate trench portions which are provided from the upper surface of the semiconductor substrate to the inside of the semiconductor substrate, arranged side by side on the upper surface of the semiconductor substrate in the first direction, and arranged to face the plurality of first gate trench portions in the second direction, wherein the mesa facing region is arranged between the plurality of first gate trench portions and the plurality of second gate trench portions” is further obvious over the combination of references because it merely involves providing a set of second gate trench portions identical to first gate trench portions on the other side of Mesa facing region (see annotated Fig. 1D of Chang above)
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include mesa facing region with source contacts and away from the mesas as taught by Okumura and Chang for the reasons applied in the rejection of claim 1 above.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Carta et. al, U.S. Pat. Pub. 2006/0214242, hereafter Carta, in view of Okumura et. al., U.S. Pat. 6,060,747, hereafter Okumura (of record), and further in view of Chang et. al., U.S. Pat. 8,431,457, hereafter Chang, and further in view of Yeldinak et. al., U.S. Pat. 8,564,024, hereafter Yeldinak
Regarding claim 11, Carta in view of Okumura in view of Chang discloses everything as applied above. Carta in view of Okumura in view of Chang fails to explicitly disclose further comprising a gate runner which is provided above the upper surface of the semiconductor substrate to overlap the plurality of first gate trench portions and connected to the plurality of first gate trench portions.
However, Yeldinak discloses (Fig. 8) further comprising a gate runner [Gate Poly Runner] which is provided above the upper surface of the semiconductor substrate [104] to overlap the plurality of first gate trench portions [126] and connected to the plurality of first gate trench portions [126].
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to replace a trench based gate runner of Chang with one of Yeldinak because Yeldinak teaches (Col.1, lines 63-67) that such a structure may increase breakdown voltage of the power device.
Regarding claim 12, Carta in view of Okumura in view of Chang in view of Yeldinak fails to explicitly disclose wherein the source region is also provided at a position overlapping the gate runner in the first mesa portion.
However, it would have been obvious to one having ordinary skill in the art prior to effective date of the instant application to arrange the source region also at a position overlapping the gate runner in the first mesa portion because the source region is merely a body contact of first conductivity type which can be arranged where convenient. In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice) (MPEP, latest Edition, 2144.04.VI.C)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VICTOR V BARZYKIN/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893