DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Election/Restrictions
5. Applicant’s election without traverse of Species III, Claims 1-14 in the reply filed on 12/09/2025 is acknowledged.
Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/09/2025.
Specification
6. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Silicon Carbide Semiconductor Device for Power Control Applications”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-5 and 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hecht, Christian et al. (Pub No. US 20140264374 A1) (hereinafter, Hecht).
Hecht, Figs 2A-2D: Semiconductor substrate comprising of (1) depositing SiC epitaxial layer on SiC dispenser wafer, (2) implanting ions, (3) bonding acceptor wafer to epitaxial layer and (4) splitting the epitaxial layer
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Re Claim 1, Hecht teaches a semiconductor substrate comprising:
a hexagonal SiC single crystal layer (Silicon carbide dispenser wafer and/or remaining epitaxial layer underneath implant zone 240; 210/220; Fig 2A; ¶[0045]; Note: Hexagonal SiC may be used per ¶¶[0029 - 0030]);
an SiC epitaxial growth layer (Silicon carbide epitaxial layer; 220; Fig 2A; ¶[0045]) disposed on an Si plane (Silicon face; 212; Fig 2A; ¶[0045]) of the SiC single crystal layer; and
an SiC polycrystalline growth layer (Carrier/acceptor wafer; 250; Fig 2D; ¶[0045]) disposed on a C plane (Carbon face of epitaxial layer 260; Fig 2D; ¶[0045]) opposite to the Si plane of the SiC single crystal layer.
Re Claim 2, Hecht teaches the semiconductor substrate according to claim 1, wherein the SiC single crystal layer ((Silicon carbide dispenser wafer and/or remaining epitaxial layer underneath implant zone 240; 210/220; Fig 2A; ¶[0045]; Note: Hexagonal SiC may be used per ¶¶[0029 - 0030]) comprises a single crystal SiC thin layer (Remaining epitaxial layer underneath implant zone, i.e. 4H-SiC single-crystal SiC; 220; ¶[0028]).
Re Claim 3, Hecht teaches the semiconductor substrate according to claim 2, wherein
the single crystal SiC thin layer (Remaining epitaxial layer underneath implant zone, i.e. 4H-SiC single-crystal SiC; 220; ¶[0028]) comprises a first ion implantation layer (Implant zone; 240; Fig 2B; ¶[0045]).
Re Claim 4, Hecht teaches the semiconductor substrate according to claim 3, wherein
the first ion implantation layer (Implant zone; 240; Fig 2B; ¶[0045]) comprises a hydrogen ion implantation layer (Hydrogen may be used an ion implantation species; 240; Fig 2B; ¶[0037]).
Re Claim 5, Hecht teaches the semiconductor substrate according to claim 4, wherein
the single crystal SiC thin layer (Remaining epitaxial layer underneath implant zone, i.e. 4H-SiC single-crystal SiC; 220; ¶[0028]) comprises a weakened layer (Per ¶[0042] crystal bonds in the implant zone may be weakened by the implanted ions) of the hydrogen ion implantation layer (Hydrogen may be used an ion implantation species; 240; Fig 2B; ¶[0037]).
` Re Claim 10, Hecht teaches the semiconductor substrate according to claim 1, wherein
the Si plane (Silicon face; 212; Fig 2A; ¶[0045]) of the SiC single crystal layer (Silicon carbide dispenser wafer and/or remaining epitaxial layer underneath implant zone 240; 210/220; Fig 2A; ¶[0045]; Note: Hexagonal SiC may be used per ¶¶[0029 - 0030]) is a [0001] oriented plane of 4H-SiC (Silicon face may have miller indices 0001 comprising of 4H-SiC; ¶¶[0028, 0030]), and a C plane (Carbon face of epitaxial layer 260; Fig 2D; ¶[0045]) opposite to the Si plane of the SiC single crystal layer is a [000-1] oriented plane of 4H-SiC (Carbon face may have miller indices 000-1 comprising of 4H-SiC; ¶¶[0028, 0030]).
Re Claim 11, Hecht teaches the semiconductor substrate according to claim 2, wherein
the Si plane (Silicon face; 212; Fig 2A; ¶[0045]) of the SiC single crystal layer (Silicon carbide dispenser wafer and/or remaining epitaxial layer underneath implant zone 240; 210/220; Fig 2A; ¶[0045]; Note: Hexagonal SiC may be used per ¶¶[0029 - 0030]) is a [0001] oriented plane of 4H-SiC (Silicon face may have miller indices 0001 comprising of 4H-SiC; ¶¶[0028, 0030]), and a C plane (Carbon face of epitaxial layer 260; Fig 2D; ¶[0045]) opposite to the Si plane of the SiC single crystal layer is a [000-1] oriented plane of 4H-SiC (Carbon face may have miller indices 000-1 comprising of 4H-SiC; ¶¶[0028, 0030]).
Re Claim 12, Hecht teaches the semiconductor substrate according to claim 1, wherein
the SiC single crystal layer (Silicon carbide dispenser wafer and/or remaining epitaxial layer underneath implant zone 240; 210/220; Fig 2A; ¶[0045]; Note: Hexagonal SiC may be used per ¶¶[0029 - 0030]) can be reused (Dispenser wafer 210 may be reused; ¶[0049]) by being removed from the epitaxial growth layer (Silicon carbide epitaxial layer; 220; Fig 2A; ¶[0045]).
Re Claim 13, Hecht teaches the semiconductor device (Electrical silicion carbide device, i.e. MOSFET; ¶[0059]) comprising the semiconductor substrate (Silicon carbide manufactured substrate may be used for a MOSFET; ¶¶[0057 - 0059]) according to claim 1.
Re Claim 14, Hecht teaches the semiconductor device according to claim 13 wherein
the semiconductor device (Electrical silicion carbide device, i.e. MOSFET; ¶[0059]) comprises at least one or a plurality of transistors selected from the group consisting of an SiC Schottky barrier diode, an SiC-MOSFET, an SiC bipolar junction transistor, an SiC diode, an SiC thyristor, and an SiC insulated gate bipolar transistor.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hecht, Christian et al. (Pub No. US 20140264374 A1) (hereinafter, Hecht) as applied to claim 1 above, and further in view of Shimizu, Tatsuo et al. (Pub No. US 20160087036 A1) (hereinafter, Shimizu).
Shimizu, Figs 12-13: Forming second ion implantation layer
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Re Claim 6, Hecht does not teach the semiconductor substrate according to claim 3, wherein
the SiC single crystal layer comprises a second ion implantation layer.
In the same field of endeavor, Shimizu teaches the semiconductor substrate according to claim 3, wherein
the SiC single crystal layer (SiC layers; 10/10a/10b; Figs 12-13; ¶¶[0102 - 0104]) comprises a second ion implantation layer (N-type impurity region; 24; Figs 12-13; ¶[0102]; Note: per ¶[0100] p-type impurity ions are implanted into drift layer 10b, the first ion implantation layer).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the SiC single crystal layer comprising a second ion implantation laye as taught by Shimizu, with the semiconductor substrate as taught by Hecht. One would have been motivated to do this with a reasonable expectation of success because a semiconductor device using SiC has the problem of having a high contact resistance between a. SiC layer and a contact electrode in a semiconductor device. The contact resistance is high, supposedly because the concentration and the activation rate of the impurity in the SiC are low, therefore a second ion implantation layer would yield lower contact resistance between the SiC layer and contact electrode (Shimizu; ¶[0004]).
Re Claim 8, Hecht does not teach the semiconductor substrate according to claim 6, wherein
the second ion implantation layer comprises a phosphorus ion implantation layer.
In the same field of endeavor, Shimizu teaches the semiconductor substrate according to claim 6, wherein
the second ion implantation layer (N-type impurity region; 24; Figs 12-13; ¶[0102]) comprises a phosphorus ion implantation layer (N-type impurity for 24 may be P (Phosphorous); ¶[0102]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second ion implantation layer comprising a phosphorus ion implantation layer, as taught by Shimizu, with the semiconductor substrate as taught by Hecht. One would have been motivated to do this with a reasonable expectation of success because phosphorous offers higher electrical activation rates than nitrogen at the same concentrations, and is suited for semiconductor devices such as MOSFET or Diodes.
Re Claim 9, Hecht does not teach the semiconductor substrate according to claim 7, wherein
the second ion implantation layer comprises a phosphorus ion implantation layer.
In the same field of endeavor, Shimizu teaches the semiconductor substrate according to claim 7, wherein
the second ion implantation layer (N-type impurity region; 24; Figs 12-13; ¶[0102]) comprises a phosphorus ion implantation layer (N-type impurity for 24 may be P (Phosphorous); ¶[0102]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the second ion implantation layer comprising a phosphorus ion implantation layer, as taught by Shimizu, with the semiconductor substrate as taught by Hecht. One would have been motivated to do this with a reasonable expectation of success because phosphorous offers higher electrical activation rates than nitrogen at the same concentrations, and is suited for semiconductor devices such as MOSFET or Diodes.
Allowable Subject Matter
11. Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the closest prior art Hecht, Christian et al. (Pub No. US 20140264374 A1) (hereinafter, Hecht) in view of Shimizu, Tatsuo et al. (Pub No. US 20160087036 A1) (hereinafter, Shimizu) either singularly or in combination fails to anticipate or render obvious
“The semiconductor substrate according to claim 6, wherein
the second ion implantation layer is disposed between the first ion implantation layer and the SiC polycrystalline growth layer,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, referring to Figs 12-13, Shimizu teaches a second ion implantation layer which is not disposed between a first ion implantation layer and a SiC polycrystalline growth layer. Instead, Shimizu teaches a Nickel or Aluminum barrier layer below the second ion implantation layer. The SiC polycrystalline growth layer (semiconductor) of Hecht would not generate a predictable result if substituted with the Nickel barrier layer (metal) of Shimizu, i.e. the utility of SiC polycrystalline growth layer requires that it be grown on the C plane of the SiC thin layer, whereas Nickel could not be substituted in this process. Therefore, the materially different properties between a metal and semiconductor yield a different functionality of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Fujibayashi, Hiroaki et al. (Pub No. US 20120181550 A1) discloses a compound semiconductor substrate includes a first substrate and a second substrate made of single crystal silicon carbide. In each of the first substrate and the second substrate, one surface is a (000-1) C-face and an opposite surface is a (0001) Si-face. The first substrate and the second substrate are bonded to each other in a state where the (0001) Si-face of the first substrate and the (0001) Si-face of the second substrate face each other, and the (000-1) C-face of the first substrate and the (000-1) C-face of the second substrate are exposed.
[2] Aketa, Masatoshi et al. (Pub No. WO 2012157679 A1) discloses a Schottky electrode contacting a surface of the semiconductor layer. The semiconductor layer includes: a drift layer that forms the surface of the semiconductor layer; and a high-resistance layer formed on a surface layer part of the drift layer, and having higher resistance than the drift layer. The high-resistance layer is formed by injecting impurity ions from the surface of the semiconductor layer, followed by an annealing process at below 1500ºC.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817