DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 7, 9, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaoka et al. (PG Pub. No. US 2022/0044970 A1) in view of Koike et al. (Foreign patent No. JP 2018-182129 A, machine translation provided).
Regarding claim 1, Nagaoka teaches a manufacturing method of a semiconductor apparatus, comprising:
preparing a wafer (¶ 0174: W) on which an adhesion layer (¶ 0186: 26) is provided in an outer peripheral region of a front surface (fig. 3: 26 provided in an outer peripheral front surface of W);
applying a protective tape (¶ 0183: protective film 22; since protective film is adhered to W, it meets the broadest reasonable interpretation of “protective tape”) on the front surface of the wafer (fig. 3: 22 applied on front surface 2 of W), wherein the protective tape is applied on the adhesion layer (fig. 3: 2 applied on 26); and
grinding a back surface of the wafer while holding the wafer by a grinding apparatus (¶¶ 0171, 0221 & figs. 10-11, 17: back surface 4 of W ground while holding W by non-illustrated grinding apparatus).
Nagaoka fails to explicitly teach the method further comprises planing a front surface of the protective tape, and the step of grinding the back surface of the wafer includes holding the wafer by the grinding apparatus through the protective tape.
Koike teaches a manufacturing method of a semiconductor apparatus, the method including planing a front surface of a protective tape (¶¶ 0040, 0045 & figs. 3A-3B: front side of protective tape 9 planarized with cutting tool 2), and grinding a back surface of a wafer while holding the wafer by a grinding apparatus through the protective tape (¶ 0050 & fig. 4: back surface 1b of wafer 1 ground while holding front surface of 1 by grinding apparatus 10 through tape 9).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to hold the wafer by the grinding apparatus of Nagaoka through a planed protective film, as a means to protect wafer the wafer while reducing to a desired thickness (Koike, ¶ 0005), and avoiding a problem that the height of the back surface of the wafer fluctuates and processing accuracy deteriorates (Koike, ¶ 0005).
Regarding claim 2, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, wherein
the outer peripheral region is a region surrounding a central region in which a semiconductor device is provided on the front surface of the wafer (Nagaoka, figs. 1-3: peripheral region of W including 26 surrounds device area 6 on front surface of W).
Regarding claim 3, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 2, wherein
a width of the outer peripheral region is 1 mm or more and 3 mm or less (Nagaoka, ¶ 0177 & figs. 2-3: 26 applied to marginal area 10, which includes a range of 1-3 mm).
Although Nagaoka in view of Koike does not explicitly teach a width of the outer peripheral region is 2 mm or more and 6 mm or less, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of “2 mm or more and 6 mm or less” overlaps the range disclosed by Nagaoka.
Regarding claim 7, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, comprising a protective tape (Nagaoka, 22) adhered to an adhesion layer (Nagaoka, 26), the protective tape (Nagaoka, 22) also adhered to a wafer (Nagaoka, fig. 3 among others: 22 adhered to 26 and wafer W).
Nagaoka in view of Koike does not teach an adhesive strength of the protective tape to the adhesion layer is greater than an adhesive strength of the protective tape to the wafer.
However, Nagaoka teaches removing both the protective tape and the adhesive layer from the wafer (Nagaoka, fig. 11: 22 and 26 removed from W).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the adhesive strength between the protective tape and the adhesive layer, as a means to remove both the protective tape and the adhesive layer from the wafer in a single process step, minimizing manufacturing steps and optimizing manufacturing efficiency.
Furthermore, it has been held that “[w]hen there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the known options within his or her technical grasp." KSR, 550 U.S. at 421, 82 USPQ2d at 1397. In the instant case, there are only three solutions to the problem of removing the protective tape and the adhesive layer from the wafer: an adhesive strength of the protective tape to the adhesion layer is the same as, greater than, or less than an adhesive strength of the protective tape to the wafer. Accordingly, it would have been within the technical grasp of said artisan to configure an adhesive strength of the protective tape to the adhesion layer to be greater than an adhesive strength of the protective tape to the wafer.
Regarding claim 9, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, wherein
the adhesion layer is a resist (Nagaoka, ¶¶ 0104, 0195: adhesive layer 26 is sensitive to radiation, meeting the broadest reasonable interpretation of ‘resist’).
Regarding claim 12, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, wherein
the preparing the wafer has forming the adhesion layer on an entire circumference of the wafer in the outer peripheral region (Nagaoka, ¶ 0186: 26 formed only in peripheral marginal area 10 of W; since Nagaoka teaches 22 is circular, 26 is formed in a peripheral area of 22, 26 meets the broadest reasonable interpretation of “forming the adhesion layer on an entire circumference of the wafer”).
Regarding claim 14, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, comprising,
after the grinding the back surface of the wafer, removing the protective tape (Nagaoka, fig. 6: 22 removed).
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaoka in view of Koike as applied to claims 2-3 above, and further in view of Gambino et al. (PG Pub. No. US 2015/0132527 A1).
Regarding claims 4-5, Nagaoka in view of Koike teaches the manufacturing methods of the semiconductor apparatus according to claims 2 and 3, comprising an outer peripheral edge of the adhesion layer and an outer peripheral edge of the wafer on the front surface of the wafer (Nagaoka, fig. 3: respective outer edges of 26 and W).
Nagaoka in view of Koike does not teach wherein the outer peripheral edge of the adhesion layer is farther inward than an outer peripheral edge of the wafer.
Gambino teaches an adhesion layer (¶ 0020: 20) provided in an outer peripheral region of a front wafer surface (¶ 0019 & fig. 2a: 20 provided in an outer peripheral region of a front surface of wafer 16b), wherein an outer peripheral edge of the adhesion layer is farther inward than an outer peripheral edge of the wafer (fig. 2a: before a grinding process, outer peripheral edge of 20 is farther inward than an outer peripheral edge of 16b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to provide the adhesion layer inward from the wafer edge, as a means to utilize the grinding method with wafers having curved outer edges, such that the wafers can be handled outside of an active device region. In addition, minimizing the size of the adhesion layer reduces risk of damage to the substrate (Nagaoka, ¶ 0089).
Regarding claim 6, Nagaoka in view of Koike and Gambino teaches the manufacturing method of the semiconductor apparatus according to claim 4, wherein
a width of the outer peripheral region is 1 mm or more and 3 mm or less (Nagaoka, ¶ 0177 & figs. 2-3: 26 applied to marginal area 10, which includes a range of 1-3 mm).
Although Nagaoka in view of Koike and Gambino does not explicitly teach a width of the outer peripheral region is 2 mm or more and 6 mm or less, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). In the instant case, the claimed range of “2 mm or more and 6 mm or less” overlaps the range disclosed by Nagaoka.
Claims 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaoka in view of Koike as applied to claim 1 above, and further in view of Priewasser et al. (PG Pub. No. US 2022/0148905 A1).
Regarding claim 8, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, comprising an adhesion layer (Nagaoka, 26).
Nagaoka in view of Koike does not teach the adhesion layer is an organic thin film.
Priewasser teaches an adhesion layer (¶ 0042: 2, similar to 26 of Nagaoka) comprising an organic thin film (¶¶ 0053-0054: 2 is a thin film comprising organic material).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the adhesive layer of Nagaoka in view of Koike with an organic thin film, as a means to optimize removal of the protective film (Priewasser, ¶ 0097 & fig. 2E).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, an organic thin film is a suitable material to provide adhesive between a wafer and a protective tape, as evidenced by Priewasser.
Regarding claim 13, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, wherein a thickness of the adhesion layer is greater than 0 μm (Nagaoka, fig. 3: 26 is greater than 0 µm).
Nagaoka in view of Koike does not teach a thickness of the adhesion layer is 20 μm or less.
Priewasser teaches an adhesion layer (¶ 0042: 2, similar to 26 of Nagaoka) comprising a thickness of 50 μm or less (¶ 0053: adhesive layer 2 has a thickness of 5 to 50 μm).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the adhesive layer thickness of Nagaoka in view of Koike, as a means to accommodate active device features (Priewasser, ¶ 0052 & fig. 1D among others).
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, the general conditions of adhesive layer thickness is disclosed by Priewasser, such that arriving at the claimed range of “greater than 0 μm, and 20 μm or less” would be a matter of routine skill.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Nagaoka in view of Koike as applied to claim 1 above, and further in view of Patten et al. (PG Pub. No. US 2015/0303171 A1).
Regarding claim 10, Nagaoka in view of Koike teaches the manufacturing method of the semiconductor apparatus according to claim 1, comprising an adhesion layer (Nagaoka, 26).
Nagaoka in view of Koike not teach wherein the adhesion layer is a polyimide film.
Patten teaches an adhesion layer formed of polyimide (¶ 0022: adhesive 12 formed of polyimide material).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the adhesive layer of Nagaoka in view of Koike with polyimide, as a means to provide a temporary bond to the wafer during the grinding step (Patten, ¶ 0022).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, a polyimide film is a suitable material to provide adhesive to a wafer during a grinding step, as evidenced by Patten.
Regarding claim 11, Nagaoka in view of Koike and Patten teaches the manufacturing method of the semiconductor apparatus according to claim 10, wherein
the preparing the wafer has forming the adhesion layer on at least half a circumference of the wafer in the outer peripheral region (Nagaoka, ¶ 0186: 26 formed only in peripheral marginal area 10 of W; since Nagaoka teaches 22 is circular, 26 is formed in a peripheral area of 22, 26 meets the broadest reasonable interpretation of “forming the adhesion layer on an entire circumference of the wafer”).
Response to Arguments
Applicant’s arguments, see page 7, filed 6/3/2026, with respect to the objection to the title have been fully considered and are persuasive. Accordingly, the objection to the specification has been withdrawn.
Applicant’s arguments with respect to the 35 USC § 103 rejections of claims 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/Examiner, Art Unit 2818
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