DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 10, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamano et. al., U.S. Pat. Pub. 2019/0287964, hereafter Yamano, in view of Shoji et. al., U.S. Pat. Pub. 2021/0151589, hereafter Shoji.
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Regarding claim 1, Yamano discloses (Figs 38,39 a semiconductor device comprising:
one or more transistor portions [70] and one or more diode portions [80] provided at different positions in a top view;
a semiconductor substrate [10] provided with the one or more transistor portions [70] and the one or more diode portions [80];
an upper surface electrode [52] (see, e.g., Fig. 20) arranged above the semiconductor substrate [10]; and
one or more first mark portions [99] arranged above the upper surface electrode, each of the one or more first mark portions [99] (see annotated Fig. 39A above), wherein each of the one or more first mark portions has a concave shape [99] (see annotated Fig 39A) or a convex shape (see a similar feature [98] in Fig 38A) in the top view or in a depth direction of the semiconductor substrate [10].
Yamano fails to explicitly disclose wherein each of the one or more first mark portions being arranged so as to straddle only one of the one or more transistor portions and only one of the one or more diode portions in the top view.
However, Shoji discloses (Fig. 3) wherein each of the one or more first mark portions [110] being arranged so as to straddle only one of the one or more transistor portions [70] and only one of the one or more diode portions [80] in the top view.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the width of the alignment mark of Yamano such that this limitation is satisfied because Yamano teaches (p. 8, Table 1, second row) a sum of widths D3 of Transistor portion [70] and D2 of diode portion close to the contact width D1 (1100 um, par. [0152]) and that the relative sizes of contact diode, and transistor portions can be optimized to reduce thermal fatigue in a junction (abstract). Optimization of a result effective variable is usually considered obvious. Furthermore, this
Limitation can be met by making a small adjustment of the mark of Yamano.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to make a small length adjustment (making the mark a little bit longer) of the one or more first mark portions that would make it meet this limitation because it was held that changing relative dimensions is within the ability of one having ordinary skill in the art (MPEP, 2144.04.A, and case law therein).
Regarding claim 2, Yamano in view of Shoji discloses everything as applied above. Yamano further discloses (Fig. 39A) wherein
each of the one or more transistor portions [70] and each of the one or more diode portions [80] are arranged side by side alternately along a first direction <x> in the top view, and
a length [D2] of each of the one or more first mark portions in the first direction is smaller than a sum of lengths [D2 +D3] of one of the one or more transistor portions [70] and one of the one or more diode portions [80] in the first direction “x”.
Regarding claim 3, Yamano in view of Shoji discloses everything as applied above. Yamano further discloses further comprising:
a protective film [95] (par. [0179]) arranged abo the upper surface electrode [52], wherein the one or more first mark portions [99] are provided in the protective film [95] (par. [0095]).
Regarding claim 4, Yamano in view of Shoji discloses everything as applied above. Yamano further discloses (Fig. 38) wherein each of the one or more transistor portions [70] and each of the one or more diode portions [80] are arranged side by side alternately along a first direction (x) in the top view,
the protective film [95] comprises a first extending portion (the portion containing the convex shape marks [98]) extending along the first direction [x], and
the one or more first mark portions [98] protrude from the first extending portion in a second direction [y] different from the first direction [x] in the top view (Note that the rejection of claim 1 above also applies to the embodiment of Fig.38, these are convex shape marks, as opposed to concave shape marks).
Regarding claim 10, Yamano discloses (Figs. 39A, 39B) a semiconductor module comprising:
a semiconductor device [100];
an electrical circuit [7] (not shown, see Fig. 32); and
a wire [2a], [2b], [2c] connecting the semiconductor device and the electrical circuit [7],
the semiconductor device comprises:
one or more transistor portions [70] and one or more diode portions [80] provided at different positions in a top view;
a semiconductor substrate [10] provided with the one or more transistor portions [70] and the one or more diode portions [80];
an upper surface electrode [52] (see, e.g., Fig. 20) arranged above the semiconductor substrate [10]; and
one or more first mark portions [99] arranged upper than the upper surface electrode, each of the one or more first mark portions [99] (see annotated Fig. 39A above), wherein each of the one or more first mark portions has a concave shape [99] (see annotated Fig 39A) or a convex shape (see a similar feature [98] in Fig 38A) in the top view or in a depth direction of the semiconductor substrate [10].
Yamano fails to explicitly disclose wherein each of the one or more first mark portions being arranged so as to straddle only one of the one or more transistor portions and only one of the one or more diode portions in the top view.
However, Shoji discloses (Fig. 3) wherein each of the one or more first mark portions [110] being arranged so as to straddle only one of the one or more transistor portions [70] and only one of the one or more diode portions [80] in the top view.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the width of the alignment mark of Yamano such that this limitation is satisfied because Yamano teaches (p. 8, Table 1, second row) a sum of widths D3 of Transistor portion [70] and D2 of diode portion close to the contact width D1 (1100 um, par. [0152]) and that the relative sizes of contact diode, and transistor portions can be optimized to reduce thermal fatigue in a junction (abstract). Optimization of a result effective variable is usually considered obvious. Furthermore, this
Limitation can be met by making a small adjustment of the mark of Yamano.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to make a small length adjustment (making the mark a little bit longer) of the one or more first mark portions that would make it meet this limitation because it was held that changing relative dimensions is within the ability of one having ordinary skill in the art (MPEP, 2144.04.A, and case law therein).
Regarding claim 13, Yamano discloses (Figs 38A, 38B, 39A, 39B) a method of manufacturing a semiconductor device comprising one or more transistor portions [70] and one or more diode portions [80] provided at different positions in a top view, comprising:
forming the one or more transistor portions [70] and the one or more diode portions [80] on a semiconductor substrate [10];
forming an upper surface electrode [52] (see, e.g., Fig. 20) above the semiconductor substrate [10]; and
forming one or more first mark portions [ 99] arranged above the upper surface electrode [52], wherein each of the one or more first mark portions [99] has a concave shape or a convex shape (convex shape of the mark [98] is shown in Fig. 38A) in the top view or in a depth direction of the semiconductor substrate [10].
Yamano fails to explicitly disclose wherein each of the one or more first mark portions being arranged so as to straddle only one of the one or more transistor portions and only one of the one or more diode portions in the top view (Fig. 39B, one or more mark portions [99] only overlaps the diode portion [80]).
However, Shoji discloses (Fig. 3) wherein each of the one or more first mark portions [110] being arranged so as to straddle only one of the one or more transistor portions [70] and only one of the one or more diode portions [80] in the top view.
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the width of the alignment mark of Yamano such that this limitation is satisfied because Yamano teaches (p. 8, Table 1, second row) a sum of widths D3 of Transistor portion [70] and D2 of diode portion close to the contact width D1 (1100 um, par. [0152]) and that the relative sizes of contact diode, and transistor portions can be optimized to reduce thermal fatigue in a junction (abstract). Optimization of a result effective variable is usually considered obvious. Furthermore, this
limitation can also be met by making a small adjustment of the mark of Yamano.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to make a small length adjustment (making the mark a little bit longer) of the one or more first mark portions that would make it meet this limitation because it was held that changing relative dimensions is within the ability of one having ordinary skill in the art (MPEP, 2144.04.A, and case law therein).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yamano et. al., U.S. Pat. Pub. 2019/0287964, hereafter Yamano in view of Shoji et. al., U.S. Pat. Pub. 2021/0151589, hereafter Shoji, and further in view of Okura, U.S. Pat. Pub. 2021/0028085, hereafter Okura.
Regarding claim 5, Yamano in view of Shoji discloses everything as applied above. Yamano in view of Shoji fails to explicitly disclose wherein an upper end position of the one or more first mark portions is lower than an upper end position of the first extending portion.
However, it would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to adjust the relative height of the one or more mark portions relative to the first extending portion because Okura teaches (Figs 7,8, par. [0004]) that a height adjustment can prevents cracks in the metal electrode.
Regarding claim 6, Yamano in view of Shoji discloses everything as applied above. Yamano further discloses (Figs 38,39) wherein each of the one or more transistor portions [70] and each of the one or more diode portions [80] are arranged side by side alternately along a first direction in the top view,
the protective film [95] comprises a first extending portion (left portion of the protective layer [95] ring) extending along the first direction (x).
Yamano fails to explicitly disclose
the one or more first mark portions protrude upward from the first extending portion.
However, it would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to adjust the relative height of the one or more mark portions relative to the first extending portion because Okura teaches (Figs 7,8, par. [0004]) that a height adjustment can prevents cracks in the metal electrode.
Claims 7-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yamano et. al., U.S. Pat. Pub. 2019/0287964, hereafter Yamano, in view of Shoji et. al., U.S. Pat. Pub. 2021/0151589, hereafter Shoji, and further in view of JP-2621420, hereafter ’20.
Regarding claim 7, Yamano in view of Shoji discloses everything as applied above. Yamano further discloses (Figs 38, 39) wherein each of the one or more transistor portions [70] and each of the one or more diode portions [80] are arranged side by side alternately along a first direction (x) in the top view, the protective film [95] comprises:
a first extending portion (the right side of the hollow ring [95] in Figs (38A,39A) extending along the first direction (x) and provided with the one or more first mark portions [98], [99]; and
a second extending portion (e.g., bottom portion if the ring [95] extending along a second direction (y) different from the first direction (x) in the top view, and
Yamano in view of Shoji fails to explicitly disclose the semiconductor device further comprises one or more second mark portions provided on the second extending portion, wherein each of the one or more second mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate.
However, ’20 discloses (p. 2, “means for solving problem, Figs 1-3) the semiconductor device further comprises one or more second mark portions [4-1], [6-1] provided on the second extending portion (bottom portion), wherein each of the one or more second mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify the marks of Yamano with the teachings of marks of ’20, because ’20 teaches (p. 2, “means for solving problem, Figs 2-3) that accurate bonding becomes possible as a result of using these marks to align bond pads and bond wires.
Regarding claim 8, Yamano in view Shoji in view of ’20 discloses everything as applied above. Yamano fails to explicitly disclose wherein a length of the one or more first mark portions in the first direction is greater than a length of the one or more second mark portions in the second direction.
However, it would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to make a small length adjustment (making the mark a little bit longer) of the one or more first mark portions that would make it meet this limitation because it was held that changing relative dimensions is within the ability of one having ordinary skill in the art (MPEP, 2144.04.A, and case law therein).
Regarding claim 9, Yamano in view of Shoji discloses everything as applied above. Yamano in view of Shoji fails to explicitly disclose further comprising:
one or more third mark portions arranged above the upper surface electrode, each of the one or more third mark portions being arranged so as to overlap both one of the one or more transistor portions and one of the one or more diode portions in the top view, wherein
each of the one or more third mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate,
the one or more transistor portions and the one or more diode portions have a longitudinal dimension along a second direction in the top view, and
the one or more first mark portions and the one or more third mark portions are arranged facing each other in the second direction.
However, ‘20 discloses (p. 2, “means for solving problem, Figs 1-3) further comprising:
one or more third mark portions [4-3] arranged above the upper surface electrode (obvious over the combination of references, since these are similar marks arranged in the same layer) , each of the one or more third mark portions [4-3] being arranged so as to overlap both one of the one or more transistor portions and one of the one or more diode portions in the top view (obvious over the combination of references because marks [4-3] and [4-2] are identical and mirror each other, wherein
each of the one or more third mark portions [4-3], [6-3] has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate,
the one or more transistor portions [70] and the one or more diode portions [80] have a longitudinal dimension along a second direction in the top view (Figs 1, 3), and
the one or more first mark portions and the one or more third mark portions are arranged facing each other in the second direction (see Figs 1, 3).
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify Yamano with the teachings of mirror marks of ’20, which together with Yamano teach all limitations of the claim because ’20 teaches (p. 2, “means for solving problem, Figs 2-3) that accurate bonding becomes possible as a result of using these marks to align bond pads and bond wires.
Regarding claim 11, Yamano in view of Shoji discloses everything as applied above. Yamano further discloses (Figs 38, 39) wherein the semiconductor device further comprises:
each of the one or more transistor portions [70] and each of the one or more diode portions [80] are arranged side by side alternately along a first direction (x) in the top view,
the one or more transistor portions [70] and the one or more diode portions [80] have a longitudinal dimension along a second direction (y) in the top view, and
connecting portions [4] (Figs 26, 27) at which the wire [2] is connected to the upper surface electrode [52] are arranged facing the one or more first mark portions [98],[99] in the second direction [y]
Yamano fails to explicitly disclose
wherein the semiconductor device further comprises:
one or more second mark portions arranged above the upper surface electrode, each of the one or more second mark portions being arranged so as to straddle only one of the one or more transistor portions and only one of the one or more diode portions in the top view , wherein
each of the one or more second mark portions has a concave shape or a convex shape in
the top view or in a depth direction of the semiconductor substrate,
wherein the connecting portions are arranged facing the one or more second mark portions in the first direction.
However, these limitations are obvious over Yamano in view Shoji in view of 20’, because ’20 discloses (Figs 1-3) wherein the semiconductor device further comprises:
one or more second mark portions [4-3] (mirror marks corresponding to [98] and [99] in Yamano) arranged upper than the upper surface electrode (obvious over the combination of references, because these marks are arranged at the same level as first marks [4-2]), each of the one or more second mark portions being arranged so as to overlap both one of the one or more transistor portions [70] and one of the one or more diode portions [80] in the top view (obvious over the combination of references because second marks are mirror marks of the first marks) , wherein each of the one or more second mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate [10],
wherein the connecting portions [4] are arranged facing the one or more second mark portions in the first direction (x) (obvious over the combination of references, specifically because the mirror marks are used to align the bonding wire as indicated in Fig. 2).
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify Yamano with the teachings of mirror marks of ’20, which together with Yamano teach all limitations of the claim because ’20 teaches (p. 2, “means for solving problem, Figs 2-3) that accurate bonding becomes possible as a result of using these marks to align bond pads and bond wires.
Regarding claim 12, Yamano in view of Shoji discloses everything as applied above. Yamano in view of Shoji fails to explicitly disclose wherein the semiconductor device further comprises:
one or more third mark portions arranged above the upper surface electrode, each of the one or more third mark portions being arranged so as to straddle only one of the one or more transistor portions and only one of the one or more diode portions in the top view, wherein
each of the one or more third mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate, and
each of connecting portions at which the wire is connected to the upper surface electrode is sandwiched between one of the one or more first mark portions and one of the one or more third mark portions.
However, ’20 discloses (Figs 1, 3) wherein the semiconductor device further comprises:
one or more third mark portions [4-3] arranged above the upper surface electrode (obvious over the combination of references since these marks are arranged on the same level), each of the one or more third mark portions [4-3] being arranged so as to overlap both one of the one or more transistor portions [70] and one of the one or more diode portions [80] in the top view (obvious over the combination with Yamano reference because these marks are mirror marks to first marks [4-2], so they overlap the same portions), wherein each of the one or more third mark portions has a concave shape or a convex shape in the top view or in a depth direction of the semiconductor substrate, and
each of connecting portions [d] at which the wire is connected to the upper surface electrode is sandwiched between one of the one or more first mark portions and one of the one or more third mark portions (see annotated Fig. 39 A, bonding wires are aligned using marks, see ’20, “means for solving the problem” on p. 2).
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify Yamano in view of Shoji with the teachings of mirror marks of ’20, which together with Yamano teach all limitations of the claim because ’20 teaches (p. 2, “means for solving problem, Figs 2-3) that accurate bonding becomes possible as a result of using these marks to align bond pads and bond wires.
Response to Arguments
Applicant’s amendments and arguments, see p.9, filed 01/20/2026, with respect to objections to clams 1, 10, and 13 have been fully considered and are persuasive. The objections have been withdrawn.
Applicant's amendments and arguments filed 01/20/2026 have been fully considered but they are not persuasive. The amended claims set the mark to straddle only one of transistor portions and only one of diode portions.
The limitation, while not explicitly taught by Yamano, is taught by Shoji et. al., U.S. Pat. Pub. 2021/0151589 for mark [110] in Fig. 3. Furthermore, Yamano teaches (abstract) optimization of contact size [D1] relative to the sizes of transistor [70] and diode [80] portions to reduce thermal fatigue (see Fig. 2). The size of alignment marks to align said contacts is commensurate with the size of the contact,
Table I (middle row, p.8) discloses a device transistor portion (D3) of 710 um, diode portion of 310 um, and contact width D1 of 1100 um (par. [0152]), which is close to the sum of these two. Thus, invention as claimed represents an obvious modification of Yamano, by optimizing result-effective variable for thermal budget and to increase device reliability.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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/VICTOR V BARZYKIN/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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