DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device embodiment 2 of fig. 6 (claims 1-10, 15-20 readable thereon, claims 11-14 withdrawn) in the reply filed on 3/1/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-10, 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification as filed fails to provide sufficient written description for the second peak including a plurality of sub-peaks as recited in claims 2 and 3. Claim 1 requires the second peak as being the closest, of the peaks within the buffer region, to the lower surface of the substrate, which would be peak 210-1. However, claim 2 and 3 requires the second peak having sub-peaks, which would be peak 210-2, which is not the closest to the lower surface, therefore the specification lacks written description for such claimed limitations.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9, and similarly in claim 17, recites “the three or more doping concentration peaks include a first peak closest to the lower surface of the semiconductor substrate” at lines 2-3.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 10, 16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tamura et al. (US PGPub 2017/0271447; hereinafter “Tamura”).
Re claim 1: Tamura teaches (e.g. figs. 4, 1, and 10A) a semiconductor device, comprising: a semiconductor substrate (10) which has an upper surface (upper surface of 10; hereinafter “US”) and a lower surface (lower surface of 10; hereinafter “LS”) and is provided with a drift region (14) of a first conductivity type (N—type as shown in fig. 1); and a buffer region (20; e.g. paragraph 72) of a first conductivity type (N+ as shown in fig. 1), which is provided between the lower surface (LS) of the semiconductor substrate (10) and the drift region (14), has three or more doping concentration peaks (40-1, 40-2, 40-3, 40-4; hereinafter “3DCP”) in a depth direction of the semiconductor substrate (10), and has a higher concentration than the drift region (14), wherein the three or more doping concentration peaks (3DCP) include a deepest peak (40-4) farthest from the lower surface (LS) of the semiconductor substrate (10) and a second peak second (40-1, 40-2; hereinafter “2P”) closest to the lower surface (LS) of the semiconductor substrate (10), and a peak width (width of 2P) of the second peak is 2 times or more of a peak width (a width within 40-4) of the deepest peak (40-4) in the depth direction.
Re claim 2: Tamura teaches the semiconductor device according to claim 1, wherein the second peak (2P) includes a plurality of sub-peaks (40-1, 40-2) in the depth direction, the three or more doping concentration peaks (3DCP) include a second deepest peak (40-3) whose distance from the lower surface (LS) of the semiconductor substrate (10) is second largest (40-3 is second largest when compared to 2P), and an interval between two of the sub-peaks (40-1, 40-2) adjacent to each other in the depth direction is smaller than a distance between the second deepest peak (40-3) and the deepest peak (40-4).
Re claim 3: Tamura teaches the semiconductor device according to claim 1, wherein the second peak (2P) includes a plurality of sub-peaks (40-1, 40-2) in the depth direction, and an interval between two of the sub-peaks (40-1, 40-2) adjacent to each other in the depth direction is 2 times or less of a full width at half maximum of the deepest peak (40-4).
Re claim 4: Tamura teaches the semiconductor device according to claim 2, wherein a distribution of a doping concentration of the second peak (2P) in the depth direction has a plurality of recesses (recess between and to the left and right of 40-1 and 40-2; hereinafter “R”), and the recesses are each arranged between the respective sub-peaks (40-1, 40-2), and the doping concentration of at least one of the recesses (R) is larger than 0.1 times a maximum value of the doping concentration of the plurality of sub-peaks (40-1, 40-2).
Re claim 5: Tamura teaches the semiconductor device according to claim 4, wherein a distribution of the doping concentration of the buffer region (20) in the depth direction has a plurality of valley portions (valley between 40-3 and 40-4 and 2P; hereinafter “VP”), and the valley portions are each arranged between the respective doping concentration peaks (40-4, 40-3, 2P), the plurality of valley portions (VP) include a first valley portion (VP between 2P and 40-3; hereinafter “1VP”) closest to the lower surface (LS) of the semiconductor substrate (10), and the doping concentration of at least one of the recesses (R to the right of 40-1 as shown in fig. 4) is higher than the doping concentration of the first valley portion (1VP).
Re claim 6: Tamura teaches the semiconductor device according to claim 4, wherein a distribution of the doping concentration of the buffer region (20) in the depth direction has a plurality of valley portions (valley between 40-3 and 40-4 and 2P; hereinafter “VP”), and the valley portions (VP) are each arranged between the respective doping concentration peaks (2VP, 40-3, 40-4), the plurality of valley portions (VP) include a deepest valley portion (VP between 40-3 and 40-4; hereinafter “DVP”) closest to the upper surface (US) of the semiconductor substrate (10), and the doping concentration of at least one of the recesses (R has concentration of approximately 5E14) is 2 times or more of the doping concentration of the deepest valley portion (DVP has concentration of approximately 2E14).
Re claim 10: Tamura teaches the semiconductor device according to claim 2, wherein a number of the sub-peaks (40-1, 40-2) in the second peak is four or less.
Re claim 16: Tamura teaches the semiconductor device according to claim 1, wherein the peak width of the second peak (2P) is 5 times or less of the peak width of the deepest peak (40-4).
Re claim 18: Tamura teaches the semiconductor device according to claim 3, wherein a distribution of a doping concentration of the second peak (2P) in the depth direction has a plurality of recesses (recess between and to the left and right of 40-1 and 40-2; hereinafter “R”), and the recesses are each arranged between the respective sub-peaks (recess between 40-1 and 40-2), and the doping concentration of at least one of the recesses (R) is larger than 0.1 times a maximum value of the doping concentration of the plurality of sub-peaks (40-2).
Claim(s) 1-3, 7, 8, 19, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Agata et al. (US PGPub 2019/0148500; hereinafter “Agata”).
Re claim 1: Agata teaches (e.g. figs. 1B and 2) a semiconductor device, comprising: a semiconductor substrate (10) which has an upper surface (upper surface of 10; hereinafter “US”) and a lower surface (lower surface of 10; hereinafter “LS”) and is provided with a drift region (14) of a first conductivity type (N--type as shown in fig. 1B); and a buffer region (20; e.g. paragraph 60) of a first conductivity type (N+ as discussed in paragraph 61), which is provided between the lower surface (LS) of the semiconductor substrate (10) and the drift region (14), has three or more doping concentration peaks (40-1, 40-2, 40-3, 40-4, 40-5, 40-6; hereinafter “3DCP”) in a depth direction of the semiconductor substrate (10), and has a higher concentration than the drift region (14), wherein the three or more doping concentration peaks (3DCP) include a deepest peak (40-6) farthest from the lower surface (LS) of the semiconductor substrate (10) and a second peak second (40-1, 40-2, 40-3; hereinafter “2P”) closest to the lower surface (LS) of the semiconductor substrate (10), and a peak width (width of 2P) of the second peak is 2 times or more of a peak width (a width within 40-6) of the deepest peak (40-6) in the depth direction.
Re claim 2: Agata teaches the semiconductor device according to claim 1, wherein the second peak (2P) includes a plurality of sub-peaks (40-1, 40-2, 40-3) in the depth direction, the three or more doping concentration peaks (3DCP) include a second deepest peak (40-4) whose distance from the lower surface (LS) of the semiconductor substrate (10) is second largest (40-4 is second largest when compared to 2P), and an interval between two of the sub-peaks (40-1, 40-2) adjacent to each other in the depth direction is smaller than a distance between the second deepest peak (40-4) and the deepest peak (40-6).
Re claim 7: Agata teaches the semiconductor device according to claim 2, wherein the plurality of sub-peaks (40-1, 40-2, 40-3) include a first sub-peak (40-1) closest to the lower surface (LS) of the semiconductor substrate (10), a second sub-peak (40-2) second closest to the lower surface (LS), and a third sub-peak (40-3) which is third closest to the lower surface (LS) and has a lower concentration than the second sub-peak (40-2), and a ratio of a doping concentration of the third sub-peak (40-3) to the doping concentration of the second sub-peak (40-2) is smaller than a ratio of the doping concentration of the second sub-peak (40-2) to the doping concentration of the first sub-peak (40-1).
Re claim 8: Agata teaches the semiconductor device according to claim 2, wherein the plurality of sub-peaks (40-1, 40-2, 40-3) include a first sub-peak (40-1) closest to the lower surface (LS) of the semiconductor substrate (10), a second sub-peak (40-2) second closest to the lower surface (LS), and a third sub-peak (40-3) which is third closest to the lower surface (LS) and has a lower concentration than the second sub-peak (40-2), and a distance between the second sub-peak (40-2) and the third sub-peak (40-3) in the depth direction is larger than a distance between the first sub-peak (40-1) and the second sub-peak (40-2) in the depth direction.
Re claim 3: Agata teaches the semiconductor device according to claim 1, wherein the second peak (2P) includes a plurality of sub-peaks (40-1, 40-2, 40-3) in the depth direction, and an interval between two of the sub-peaks (40-1, 40-2) adjacent to each other in the depth direction is 2 times or less of a full width at half maximum of the deepest peak (40-6).
Re claim 19: Agata teaches the semiconductor device according to claim 3, wherein the plurality of sub-peaks (40-1, 40-2, 40-3) include a first sub-peak (40-1) closest to the lower surface (LS) of the semiconductor substrate (10), a second sub-peak (40-2) second closest to the lower surface (LS), and a third sub-peak (40-3) which is third closest to the lower surface (LS) and has a lower concentration than the second sub-peak (40-2), and a ratio of a doping concentration of the third sub-peak (40-3) to the doping concentration of the second sub-peak (40-2) is smaller than a ratio of the doping concentration of the second sub-peak (40-2) to the doping concentration of the first sub-peak (40-1).
Re claim 20: Agata teaches the semiconductor device according to claim 3, wherein the plurality of sub-peaks (40-1, 40-2, 40-3) include a first sub-peak (40-1) closest to the lower surface (LS) of the semiconductor substrate (10), a second sub-peak (40-2) second closest to the lower surface (LS), and a third sub-peak (40-3) which is third closest to the lower surface (LS) and has a lower concentration than the second sub-peak (40-2), and a distance between the second sub-peak (40-2) and the third sub-peak (40-3) in the depth direction is larger than a distance between the first sub-peak (40-1) and the second sub-peak (40-2) in the depth direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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