Prosecution Insights
Last updated: October 22, 2026
Application No. 18/356,255

SEMICONDUCTOR DEVICE

Final Rejection §102
Filed
Jul 21, 2023
Priority
Aug 12, 2022 — JP 2022-128976
Examiner
MIYOSHI, JESSE Y
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
2 (Final)
57%
Grant Probability
Moderate
3-4
OA Rounds
4m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
278 granted / 487 resolved
-10.9% vs TC avg
Strong +19% interview lift
Without
With
+18.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
30 currently pending
Career history
551
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
49.7%
+9.7% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
24.7%
-15.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 487 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-10, and 15-20 have been considered but are moot in view of the new grounds of rejection. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-10 and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi (US PGPub 2017/0271450). Re claim 1: Takahashi teaches (e.g. figs. 24 and 25) a semiconductor device, comprising: a semiconductor substrate (substrate as shown in fig. 3; hereinafter “S”) which has an upper surface (upper surface of substrate S; hereinafter “US”) and a lower surface (lower surface of S; hereinafter “LS”) and is provided with a drift region (drift region 1; e.g. paragraph 46) of a first conductivity type (N-type drift region 1; e.g. paragraph 46); and a buffer region (region of buffer layers 12a, 12b, 12c, 12d, 13; e.g. paragraphs 50-52; hereinafter “BR”) of a first conductivity type (N-type; e.g. paragraph 48), which is provided between the lower surface (LS) of the semiconductor substrate (S) and the drift region (1), has three or more doping concentration peaks (12a, 12b, 12c, 12d, 13; hereinafter “3DCP”) in a depth direction from the lower surface (LS) of the semiconductor substrate (1), and has a higher concentration (see fig. 25) than the drift region (1), wherein the three or more doping concentration peaks (3DCP) include a deepest peak (12a) farthest from the lower surface (LS) of the semiconductor substrate (S) and a second peak (12d) is second closest to the lower surface (LS) of the semiconductor substrate (S), a peak width (width of 12d) of the second peak (12d) is 2 times or more and 5 times of less of a peak width (width of 12a) of the deepest peak (12a) in the depth direction, the three or more doping concentration peaks (3DCP) include a first peak (13) closest to the lower surface (LS) of the semiconductor substrate (S), and the second peak (12d) includes a plurality of sub-peaks (12d is provided with 3 sub-peaks; hereinafter “SP”) in the depth direction. Re claim 2: Takahashi teaches the semiconductor device according to claim 1, wherein an interval between two of the plurality of sub-peaks (SP) adjacent to each other in the depth direction is smaller than a distance between a second deepest peak (12b) and the deepest peak (12a). Re claim 3: Takahashi teaches the semiconductor device according to claim 1, wherein an interval between two of the plurality of sub-peaks (SP) adjacent to each other in the depth direction is 2 times or less of a full width at half maximum of the deepest peak (12a). Re claim 4: Takahashi teaches the semiconductor device according to claim 2, wherein a distribution of a doping concentration of the second peak (12d) in the depth direction has a plurality of recesses (recess between each SP; hereinafter “R”), and the recesses are each arranged between respective one of the plurality of sub-peaks (SP), and the doping concentration of at least one of the recesses (R) is larger than 0.1 times a maximum value of the doping concentration of the plurality of sub-peaks (SP). Re claim 5: Takahashi teaches the semiconductor device according to claim 4, wherein a distribution of the doping concentration of the buffer region (BR) in the depth direction has a plurality of valley portions (valley between each 12a, 12b, 12c, 12d, 13; hereinafter “VP”), and the valley portions are each arranged between the respective doping concentration peaks (12a, 12b, 12c, 12d, 13), the plurality of valley portions (VP) include a first valley portion (VP between 12d and 13 as shown in fig. 25; hereinafter “1VP”) closest to the lower surface (LS) of the semiconductor substrate (S), and the doping concentration of at least one of the recesses (R as shown in fig. 25) is higher than the doping concentration of the first valley portion (1VP). Re claim 6: Takahashi teaches the semiconductor device according to claim 4, wherein a distribution of the doping concentration of the buffer region (BR) in the depth direction has a plurality of valley portions (valley between each 12a, 12b, 12c, 12d, 13; hereinafter “VP”), and the valley portions (VP) are each arranged between the respective doping concentration peaks (12a, 12b, 12c, 12d, 13), the plurality of valley portions (VP) include a deepest valley portion (VP between 12a and 12b; hereinafter “DVP”) closest to the upper surface (US) of the semiconductor substrate (S), and the doping concentration of at least one of the recesses (R has concentration of approximately 5E14) is 2 times or more of the doping concentration of the deepest valley portion (DVP has concentration of approximately 2E14). Re claim 7: Takahashi teaches the semiconductor device according to claim 2, wherein the plurality of sub-peaks (SP) include a first sub-peak (right SP of 12d of fig. 25; hereinafter “1SP”) closest to the lower surface (LS) of the semiconductor substrate (S), a second sub-peak (the middle SP of 12d of fig. 25; hereinafter “2SP”) second closest to the lower surface (LS), and a third sub-peak (left SP of 12d of fig. 25; hereinafter “3SP”) which is third closest to the lower surface (LS) and has a lower concentration (portion of 3SP has a portion which is lower than 2SP) than the second sub-peak (2SP), and a ratio of a doping concentration of the third sub-peak (3SP) to the doping concentration of the second sub-peak (2SP) is smaller than a ratio of the doping concentration of the second sub-peak (2SP) to the doping concentration of the first sub-peak (1SP). Re claim 8: Takahashi teaches the semiconductor device according to claim 2, wherein the plurality of sub-peaks (SP) include a first sub-peak (right SP of 12d of fig. 25; hereinafter “1SP”) closest to the lower surface (LS) of the semiconductor substrate (S), a second sub-peak (the middle SP of 12d of fig. 25; hereinafter “2SP”) second closest to the lower surface (LS), and a third sub-peak (left SP of 12d of fig. 25; hereinafter “3SP”) which is third closest to the lower surface (LS) and has a lower concentration (portion of 3SP has a portion which is lower than 2SP) than the second sub-peak (2SP), and a distance between the second sub-peak (2SP) and the third sub-peak (3SP) in the depth direction is larger than a distance between the first sub-peak (1SP) and the second sub-peak (2SP) in the depth direction. Re claim 9: Takahashi teaches the semiconductor device according to claim 2, wherein the plurality of sub-peaks (SP) include a first sub-peak (right SP of 12d of fig. 25; hereinafter “1SP”) closest to the lower surface (LS) of the semiconductor substrate (S), and the interval between two adjacent ones in the depth direction of the plurality of sub-peaks (SP) is smaller than a distance between the first peak (13) and the first sub-peak (1SP). Re claim 10: Takahashi teaches the semiconductor device according to claim 2, wherein a number of the plurality of sub-peaks (SP) in the second peak is four or less (three SP). Re claim 15: Takahashi teaches the semiconductor device according to claim 1, wherein the three or more doping concentration peaks (3DCP) include a third peak (12c) third closest to the lower surface (LS) of the semiconductor substrate (S), and a doping concentration of the second peak (12d) is lower than the doping concentration of the first peak (13) and higher (the three overlapping peaks will have a greater peak once dopant activation anneal is performed) than the doping concentration of the third peak (12c). Re claim 16: Takahashi teaches the semiconductor device according to claim 1, wherein the peak width of the second peak (12d) is 5 times or less of the peak width of the deepest peak (12a). Re claim 17: Takahashi teaches the semiconductor device according to claim 1, wherein the peak width of the second peak (12d) is 0.5 times or less of a distance between the first peak (13) and the deepest peak (12a) in the depth direction. Re claim 18: Takahashi teaches the semiconductor device according to claim 3, wherein a distribution of a doping concentration of the second peak (12d) in the depth direction has a plurality of recesses (recess between each SP of 12d; hereinafter “R”), and the recesses are each arranged between respective ones of the plurality of sub-peaks (SP), and the doping concentration of at least one of the recesses (R) is larger than 0.1 times a maximum value of the doping concentration of the plurality of sub-peaks (SP). Re claim 19: Takahashi teaches the semiconductor device according to claim 3, wherein the plurality of sub-peaks (SP) include a first sub-peak (right SP of 12d of fig. 25; hereinafter “1SP”) closest to the lower surface (LS) of the semiconductor substrate (S), a second sub-peak (middle SP of 12d of fig. 25; hereinafter “2SP”) second closest to the lower surface (LS), and a third sub-peak (left SP of 12d of fig. 25; hereinafter “3SP”) which is third closest to the lower surface (LS) and has a lower concentration than the second sub-peak (2SP), and a ratio of a doping concentration of the third sub-peak (3SP) to the doping concentration of the second sub-peak (2SP) is smaller than a ratio of the doping concentration of the second sub-peak (2SP) to the doping concentration of the first sub-peak (1SP). Re claim 20: Takahashi teaches the semiconductor device according to claim 3, wherein the plurality of sub-peaks (SP) include a first sub-peak (right SP of 12d of fig. 25; hereinafter “1SP”) closest to the lower surface (LS) of the semiconductor substrate (S), a second sub-peak (middle SP of 12d of fig. 25; hereinafter “2SP”) second closest to the lower surface (LS), and a third sub-peak (left SP of 12d of fig. 25; hereinafter “3SP”) which is third closest to the lower surface (LS) and has a lower concentration than the second sub-peak (2SP), and a distance between the second sub-peak (2SP) and the third sub-peak (3SP) in the depth direction is larger than a distance between the first sub-peak (1SP) and the second sub-peak (2SP) in the depth direction. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Jul 21, 2023
Application Filed
May 05, 2026
Non-Final Rejection mailed — §102
Jul 16, 2026
Interview Requested
Jul 22, 2026
Examiner Interview Summary
Jul 22, 2026
Applicant Interview (Telephonic)
Jul 31, 2026
Response Filed
Oct 02, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
57%
Grant Probability
76%
With Interview (+18.6%)
3y 7m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 487 resolved cases by this examiner. Grant probability derived from career allowance rate.

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