DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 8/21/2026 is acknowledged.
Applicant amended claims 1, 3, 5, 7, 10, 17, 19, and 20.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/31/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paul et al. (US 2020/0111798) (hereafter Paul).
Regarding claim 1, Paul (see upside down figures of Figs. 3A-3H) discloses a microelectronic structure comprising:
a first row of stacked nano devices (310, 320, and 330 in Fig. 3A, paragraph 0048, wherein “nanowire or nanosheet”) that includes a plurality of first stacked nano FET devices (310, 320, and 330 in Fig. 3A) and a second row of stacked nano devices (350, 360, and 370 in Fig. 3A, paragraph 0048, wherein “nanowire or nanosheet”) that includes a plurality of second stacked nano FET devices (350, 360, and 370 in Fig. 3A), wherein each of the plurality of first stacked nano FET devices (310, 320, and 330 in Figs. 3B and 3D) and each of the plurality of second stacked nano FET devices (350, 360, and 370 in Figs. 3B and 3D) includes an upper stack transistor (320 and 360 in Figs. 3B and 3D) and a lower stack transistor (330 and 370 in Figs. 3B and 3D);
a gate cut (305A and 385 in Fig. 3B, paragraphs 0056 and 0060) located between the first row of stacked nano devices 310 (Fig. 3B, paragraph 0056) and the second row stacked nano devices (360 and 370 in Fig. 3B); and
an interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G, paragraphs 0057 and 0063) located within (see Fig. 3B, wherein 392.2 is diagonally between 305A and 385; and see claim filed on 3/19/2026 does not disclose an entire interconnect contact located within the gate cut) the gate cut (305A and 385 in Fig. 3B), wherein the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) is connected to a source/drain 332a (Fig. 3F, paragraph 0044) of one of the lower stack transistors 330 (Fig. 3F), wherein the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) includes a non-uniform backside surface (see upside down figure of Fig. 3F, wherein a back surface of 394 contacting 309 and another back surface of 398 form a non-uniform backside surface), wherein the non-uniform backside surface is defined by a valley (region where 308 and 309 are formed in Fig. 3F) comprising a lower surface (back surface of 309 in Fig. 3F) and two vertical side surfaces (side surfaces of 308 in Fig. 3F) perpendicular to the lower surface (back surface of 309 in Fig. 3F), the valley (region where 308 and 309 are formed in Fig. 3F) located in the non-uniform backside surface (see upside down figure of Fig. 3F, wherein a back surface of 394 contacting 309 and another back surface of 398 form a non-uniform backside surface) of the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) where the valley (region where 308 and 309 are formed in Fig. 3F) is filled with a portion of a backside interlayer dielectric layer (308 and 309 in Fig. 3F, paragraph 0062, wherein “interlayer dielectric (ILD) material”).
Regarding claim 2, Paul further discloses the microelectronic structure of claim 1, wherein the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) includes an extension 391 (Fig. 3F) that extends under the source/drain 332a (Fig. 3F) of the lower stack transistor 330 (Fig. 3F).
Regarding claim 3, Paul further discloses the microelectronic structure of claim 2, wherein the extension 391 (Fig. 3F) of the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) has a first height (vertical length of 391 from surface contacting 332a to surface contacting 399 in Fig. 3F), when measured from a frontside surface to a backside surface, wherein interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) has a section (393, 394 and 398 in Fig. 3F) that is located adjacent to the extension 391 (Fig. 3F) of the interconnect contact, wherein an adjacent section (393, 394 and 398 in Fig. 3F) of the interconnect contact has second height (vertical length of 393, 394, and 398 from surface contacting 302 to bottom surface of 398 in Fig. 3F), when measured from a frontside surface to a backside surface.
Regarding claim 4, Paul further discloses the microelectronic structure of claim 3, wherein the second height (vertical length of 393, 394, and 398 from surface contacting 302 to bottom surface of 398 in Fig. 3F) is larger than the first height (vertical length of 391 from surface contacting 332a to surface contacting 399 in Fig. 3F), wherein the difference in the first height (vertical length of 391 from surface contacting 332a to surface contacting 399 in Fig. 3F) and the second height (vertical length of 393, 394, and 398 from surface contacting 302 to bottom surface of 398 in Fig. 3F) causes the non-uniform backside surface of the interconnect contact.
Regarding claim 19, Paul (see upside down figures of Figs. 3A-3H) discloses a method comprising:
forming a first row of stacked nano devices (310, 320, and 330 in Fig. 3A, paragraph 0048, wherein “nanowire or nanosheet”) that includes a plurality of first stacked nano FET devices (310, 320, and 330 in Fig. 3A) and forming a second row of stacked nano devices (350, 360, and 370 in Fig. 3A, paragraph 0048, wherein “nanowire or nanosheet”) that includes a plurality of second stacked nano FET devices (350, 360, and 370 in Fig. 3A), wherein each of the plurality of first stacked nano FET devices (310, 320, and 330 in Figs. 3B and 3D) and each of the plurality of second stacked nano FET devices (350, 360, and 370 in Figs. 3B and 3D) includes an upper stack transistor (320 and 360 in Figs. 3B and 3D) and a lower stack transistor (330 and 370 in Figs. 3B and 3D);
forming a gate cut (305A and 385 in Fig. 3B, paragraphs 0056 and 0060) located between the first row of stacked nano devices 310 (Fig. 3B, paragraph 0056) and the second row stacked nano devices (360 and 370 in Fig. 3B); and
forming an interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G, paragraphs 0057 and 0063) located within (see Fig. 3B, wherein 392.2 is diagonally between 305A and 385; and see claim filed on 3/19/2026 does not disclose an entire interconnect contact located within the gate cut) the gate cut (305A and 385 in Fig. 3B), wherein the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) is connected to a source/drain 332a (Fig. 3F, paragraph 0044) of one of the lower stack transistors 330 (Fig. 3F), wherein the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) includes a non-uniform backside surface (see upside down figure of Fig. 3F, wherein a back surface of 394 contacting 309 and another back surface of 398), wherein non-uniform backside surface is defined by a valley (region where 308 and 309 are formed in Fig. 3F) comprising a lower surface (back surface of 309 in Fig. 3F) and two vertical side surfaces (side surfaces of 308 in Fig. 3F) perpendicular to the lower surface (back surface of 309 in Fig. 3F), the valley (region where 308 and 309 are formed in Fig. 3F) located in the non-uniform backside surface (see upside down figure of Fig. 3F, wherein a back surface of 394 contacting 309 and another back surface of 398 form a non-uniform backside surface) located in the non-uniform backside surface of the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) where the valley (region where 308 and 309 are formed in Fig. 3F) is filled with a portion of a backside interlayer dielectric layer (308 and 309 in Fig. 3F, paragraph 0062, wherein “interlayer dielectric (ILD) material”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Paul as applied to claims 2 and 19 above, and further in view of Huang et al. (US 2021/0407999) (hereafter Huang).
Regarding claim 5, Paul discloses the microelectronic structure of claim 2, however Paul does not disclose a plurality of metal lines located on a backside of the first row of stacked nano devices and the second row of stacked nano devices.
Huang (see upside down figure of Fig. 8) discloses a plurality of metal lines (element number is not shown in Fig. 8 but see 340 in Fig. 7, paragraph 0064) located on a backside of the first row of stacked nano devices (device with 318 (Fig. 6) in Fig. 8; and see “shared-gate, stacked nanoribbon transistors” in paragraph 0034) and the second row of stacked nano devices (device with 316 in Fig. 8; and see “shared-gate, stacked nanoribbon transistors” in paragraph 0034).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul to form a plurality of metal lines located on a backside of the first row of stacked nano devices and the second row of stacked nano devices, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 6, Paul in view of Huang discloses the microelectronic structure of claim 5, however Paul does not disclose the extension of the interconnect contact extends across multiple metal lines of the plurality of metal lines.
Huang (see upside down figure of Fig. 8) discloses the extension (element number is not shown in Fig. 8 but see 332 in Fig. 7, paragraph 0060) of the interconnect contact extends across multiple metal lines of the plurality of metal lines (element number is not shown in Fig. 8 but see 340 in Fig. 7, paragraph 0064).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul to form the extension of the interconnect contact extends across multiple metal lines of the plurality of metal lines, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 7, Paul in view of Huang discloses the microelectronic structure of claim 6, however Paul does not disclose the backside interlayer dielectric layer located between the extension of the interconnect contact and the plurality of metal lines.
Huang (see upside down figure of Fig. 8) discloses the backside interlayer dielectric layer (334 and left 308 in Fig. 7, paragraph 0060) located between the extension 332 (Fig. 7, paragraph 0060) of the interconnect contact and the plurality of metal lines 340 (Fig. 7, paragraph 0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul to form the backside interlayer dielectric layer located between the extension of the interconnect contact and the plurality of metal lines, as taught by Huang, since a backside interlayer dielectric layer electrically isolates the metal lines..
Regarding claim 8, Paul in view of Huang discloses the microelectronic structure of claim 7, however Paul does not disclose the interconnect contact is connected to one of the metal lines of the plurality of metal lines.
Huang (see upside down figure of Fig. 8) discloses the interconnect contact 332 (Fig. 7, paragraph 0060) is connected to one of the metal lines of the plurality of metal lines 340 (Fig. 7, paragraph 0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul to form the interconnect contact is connected to one of the metal lines of the plurality of metal lines, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 9, Paul in view of Huang discloses the microelectronic structure of claim 8, however Paul does not disclose the backside interlayer dielectric layer is in contact with a backside surface of the extension of the interconnect contact and a side surface of the interconnect contact.
Huang (see upside down figure of Fig. 8) discloses the backside interlayer dielectric layer (334 and left 308 in Fig. 7, paragraph 0060) is in contact with a backside surface of the extension 332 (Fig. 7, paragraph 0060) of the interconnect contact and a side surface of the interconnect contact 332 (Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul to form the backside interlayer dielectric layer is in contact with a backside surface of the extension of the interconnect contact and a side surface of the interconnect contact, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 20, Paul further discloses the method of claim 19, wherein the gate cut (305A and 385 in Fig. 3B) includes a dielectric liner 305A (Fig. 3B, paragraph 0056) and a dielectric fill layer 385 (Fig. 3B, paragraph 0060), wherein an extension 391 (Fig. 3F) of the interconnect contact is in direct contact with a backside surface of the source/drain 332a (Fig. 3F) of the lower stack transistor 330 (Fig. 3F).
Paul does not disclose the extension of the interconnect contact is in direct contact with a first sidewall of the dielectric liner, wherein the interconnect contact is direct contact with a second sidewall of the dielectric liner, and wherein the first sidewall of the dielectric liner is opposite the second sidewall of the dielectric liner.
Huang (see upside down figure of Fig. 8) discloses the extension 332 (Fig. 7, paragraph 0060) of the interconnect contact is in direct contact with a first sidewall (left sidewall of middle 308 in Fig. 7) of the dielectric liner (middle 308 in Fig. 7, paragraph 0061), wherein the interconnect contact 332 (Fig. 7) is direct contact with a second sidewall (right sidewall of middle 308 in Fig. 7) of the dielectric liner (middle 308 in Fig. 7), and wherein the first sidewall (left sidewall of middle 308 in Fig. 7) of the dielectric liner is opposite the second sidewall (right sidewall of middle 308 in Fig. 7) of the dielectric liner (middle 308 in Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul to form the extension of the interconnect contact is in direct contact with a first sidewall of the dielectric liner, wherein the interconnect contact is direct contact with a second sidewall of the dielectric liner, and wherein the first sidewall of the dielectric liner is opposite the second sidewall of the dielectric liner, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Paul et al. (US 2020/0111798) (hereafter Paul), in view of Park et al. (US 2022/0415906) (hereafter Park).
Regarding claim 10, Paul (see upside down figures of Figs. 3A-3H) discloses a microelectronic structure comprising:
a first row of stacked nano devices (310, 320, and 330 in Fig. 3A, paragraph 0048, wherein “nanowire or nanosheet”) that includes a plurality of first stacked nano FET devices (310, 320, and 330 in Fig. 3A) and a second row of stacked nano devices (350, 360, and 370 in Fig. 3A, paragraph 0048, wherein “nanowire or nanosheet”) that includes a plurality of second stacked nano FET devices (350, 360, and 370 in Fig. 3A), wherein each of the plurality of first stacked nano FET devices (310, 320, and 330 in Figs. 3B and 3D) and each of the plurality of second stacked nano FET devices (350, 360, and 370 in Figs. 3B and 3D) includes an upper stack transistor (320 and 360 in Figs. 3B and 3D) and a lower stack transistor (330 and 370 in Figs. 3B and 3D);
a gate cut (305A and 385 in Fig. 3B, paragraphs 0056 and 0060) located between the first row of stacked nano devices 310 (Fig. 3B, paragraph 0056) and the second row stacked nano devices (360 and 370 in Fig. 3B), wherein the gate cut (305A and 385 in Fig. 3B) includes a dielectric liner 305A (Fig. 3B, paragraph 0056) lining a bottom (bottom of 305Ain Fig. 3B) and sides (left side of 305A contacting 315 and right side of 305A contacting 392.2 in Fig. 3B) of the gate cut (305A and 385 in Fig. 3B) on an exterior surface (left side surface of 305A contacting 306 in Fig. 3B) and lining a dielectric fill layer 385 (Fig. 3B, paragraph 0060) on an interior surface (interface between 385 and 305A in Fig. 3B); and
an interconnect contact (391-394 in Figs. 3F and 3G, paragraphs 0057 and 0063) located within the gate cut (305A and 385 in Fig. 3B; and see claim filed on 3/19/2026 does not disclose an entire interconnect contact located within the gate cut), wherein the interconnect contact (391-394 in Figs. 3F and 3G) is connected to a source/drain 332a (Fig. 3F, paragraph 0063) of one of the lower stack transistors 330 (Fig. 3F), wherein the interconnect contact (391-394 in Figs. 3F and 3G) includes a non-uniform backside surface, wherein the interconnect contact 394 (Fig. 3G) has different vertical side surfaces that are in contact with the dielectric fill layer 385 (Fig. 3G) and the dielectric liner 305B (Fig. 3G).
Paul does not disclose dielectric liner is located around the dielectric fill layer.
Park discloses dielectric liner 140 (Fig. 5, paragraph 0051) is located around the dielectric fill layer 170 (Fig. 5, paragraph 0072).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul to form dielectric liner is located around the dielectric fill layer, as taught by Park, since the source/drain areas 160A and 160B (Park, Fig. 4, paragraph 0064) may be electrically separated from the gate electrode 130 (Park, Fig. 4, paragraph 0064) via the gate spacer 140 (Park, Fig. 4, paragraph 0064).
Regarding claim 11, Paul further discloses the microelectronic structure of claim 10, wherein the interconnect contact (391-394 in Figs. 3F and 3G) includes an extension 394 (Fig. 3F) that extends under (see Fig. 3F, wherein 394 is located lower than 332a) the source/drain 372a (Fig. 3F) of the lower stack transistor 370 (Fig. 3F).
Claims 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over Paul in view of Park as applied to claim 11 above, and further in view of Huang et al. (US 2021/0407999) (hereafter Huang).
Regarding claim 12, Paul in view of Park discloses the microelectronic structure of claim 11, however Paul and Park do not disclose a plurality of metal lines located on a backside of the first row of stacked nano devices and the second row stacked nano devices.
Huang (see upside down figure of Fig. 8) discloses a plurality of metal lines (element number is not shown in Fig. 8 but see 340 in Fig. 7, paragraph 0064) located on a backside of the first row of stacked nano devices (device with 318 (Fig. 6) in Fig. 8; and see “shared-gate, stacked nanoribbon transistors” in paragraph 0034) and the second row stacked nano devices (device with 316 in Fig. 8; and see “shared-gate, stacked nanoribbon transistors” in paragraph 0034).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul in view of Park to form a plurality of metal lines located on a backside of the first row of stacked nano devices and the second row stacked nano devices, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 13, Paul in view of Park and Huang discloses the microelectronic structure of claim 12, however Paul and Park do not disclose the extension of the interconnect contact extends across multiple metal lines of the plurality of metal lines.
Huang (see upside down figure of Fig. 8) discloses the extension (element number is not shown in Fig. 8 but see 332 in Fig. 7, paragraph 0060) of the interconnect contact extends across multiple metal lines of the plurality of metal lines (element number is not shown in Fig. 8 but see 340 in Fig. 7, paragraph 0064).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul in view of Park to form the extension of the interconnect contact extends across multiple metal lines of the plurality of metal lines, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 14, Paul in view of Park and Huang discloses the microelectronic structure of claim 13, however Paul and Park do not disclose a backside interlayer dielectric layer located between the extension of the interconnect contact and the plurality of metal lines.
Huang (see upside down figure of Fig. 8) discloses a backside interlayer dielectric layer (334 and left 308 in Fig. 7, paragraph 0060) located between the extension 332 (Fig. 7, paragraph 0060) of the interconnect contact and the plurality of metal lines 340 (Fig. 7, paragraph 0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul in view of Park to form a backside interlayer dielectric layer located between the extension of the interconnect contact and the plurality of metal lines, as taught by Huang, since a backside interlayer dielectric layer electrically isolates the metal lines.
Regarding claim 15, Paul in view of Park and Huang discloses the microelectronic structure of claim 14, however Paul and Park do not disclose the interconnect contact is connected to one of the metal lines of the plurality of metal lines.
Huang (see upside down figure of Fig. 8) discloses the interconnect contact 332 (Fig. 7, paragraph 0060) is connected to one of the metal lines of the plurality of metal lines 340 (Fig. 7, paragraph 0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul in view of Park to form the interconnect contact is connected to one of the metal lines of the plurality of metal lines, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 16, Paul in view of Park and Huang discloses the microelectronic structure of claim 15, however Paul and Park do not disclose the backside interlayer dielectric layer is in contact with a backside surface of the extension of the interconnect contact and a side surface of the interconnect contact.
Huang (see upside down figure of Fig. 8) discloses the backside interlayer dielectric layer (334 and left 308 in Fig. 7, paragraph 0060) is in contact with a backside surface of the extension 332 (Fig. 7, paragraph 0060) of the interconnect contact and a side surface of the interconnect contact 332 (Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul in view of Park to form the backside interlayer dielectric layer is in contact with a backside surface of the extension of the interconnect contact and a side surface of the interconnect contact, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 17, Paul in view of Park and Huang discloses the microelectronic structure of claim 11, however Paul and Park do not disclose the extension of the interconnect contact is in direct contact with a backside surface of the source/drain of the lower stack transistor and the extension of the interconnect contact is in direct contact with a first sidewall of the dielectric liner.
Huang (see upside down figure of Fig. 8) discloses the extension 332 (Fig. 7, paragraph 0060) of the interconnect contact is in direct contact with a backside surface of the source/drain (element number is not shown in Fig. 7 but see 318 in Fig. 6, paragraph 0057) of the lower stack transistor (transistor with 318 in Fig. 7) and the extension 332 (Fig. 7, paragraph 0060) of the interconnect contact is in direct contact with a first sidewall of the dielectric liner (middle 308 in Fig. 7, paragraph 0061).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul in view of Park to form the extension of the interconnect contact is in direct contact with a backside surface of the source/drain of the lower stack transistor and the extension of the interconnect contact is in direct contact with a first sidewall of the dielectric liner, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Regarding claim 18, Paul in view of Park and Huang discloses the microelectronic structure of claim 17, however Paul and Park do not disclose the interconnect contact is direct contact with a second sidewall of the dielectric liner, wherein the first sidewall of the dielectric liner is the opposite the second sidewall of the dielectric liner.
Huang (see upside down figure of Fig. 8) discloses the interconnect contact 332 (Fig. 7, paragraph 0060) is direct contact with a second sidewall (right sidewall of middle 308 in Fig. 7) of the dielectric liner (middle 308 in Fig. 7, paragraph 0061), wherein the first sidewall (left sidewall of middle 308 in Fig. 7) of the dielectric liner (middle 308 in Fig. 7) is the opposite the second sidewall (right sidewall of middle 308 in Fig. 7) of the dielectric liner (middle 308 in Fig. 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Paul in view of Park to form the interconnect contact is direct contact with a second sidewall of the dielectric liner, wherein the first sidewall of the dielectric liner is the opposite the second sidewall of the dielectric liner, as taught by Huang, since, in the source or drain locations (Paul, paragraph 0060), conductive vias 340 (Paul, Fig. 7, paragraph 0060) and corresponding conductive lines 342 (Paul, Fig. 7, paragraph 0060) are formed to contact corresponding upper source or drain contacts 332 (Paul, Fig. 7, paragraph 0060) in the inter-layer dielectric layer 334 (Paul, Fig. 7, paragraph 0060).
Response to Arguments
1. Applicant's arguments filed 8/21/2026 have been fully considered.
2. The applicant argues (REMARKS, first paragraph in page 9) that “Neither of these features, however, discloses, teaches, or suggests "a valley comprising a lower surface and two vertical side surfaces perpendicular to the lower surface, the valley located in the backside of the interconnect contact where the valley is filled with a portion of a backside interlayer dielectric layer" as recited in claim 1.” In addition, the applicant argues (REMARKS, second paragraph in page 9) that “For at least these reasons, the cited sections of the applied reference do not disclose all of the elements of claim 1, as amended. Independent claim 19, as amended, recites similar features. Therefore, independent claims 1 and 19, and the claims that depend thereon, are patentable over the cited sections of the applied reference.” However, Paul et al. (US 2020/0111798) disclose the non-uniform backside surface is defined by a valley (region where 308 and 309 are formed in Fig. 3F) comprising a lower surface (back surface of 309 in Fig. 3F) and two vertical side surfaces (side surfaces of 308 in Fig. 3F) perpendicular to the lower surface (back surface of 309 in Fig. 3F), the valley (region where 308 and 309 are formed in Fig. 3F) located in the non-uniform backside surface (see upside down figure of Fig. 3F, wherein a back surface of 394 contacting 309 and another back surface of 398 form a non-uniform backside surface) of the interconnect contact (391-394, 398, and 399 in Figs. 3F and 3G) where the valley (region where 308 and 309 are formed in Fig. 3F) is filled with a portion of a backside interlayer dielectric layer (308 and 309 in Fig. 3F, paragraph 0062, wherein “interlayer dielectric (ILD) material”).
3. The applicant argues (REMARKS, third paragraph in page 10) that “The cited references fail to teach or suggest the "dielectric liner" recited in claim 10. The Office Action contends that the "gate cut isolation region 305B" of PAUL discloses the "dielectric liner," but the gate cut isolation region 305B does not line "a bottom and sides of the gate cut on an exterior surface and lining a dielectric fill layer on an interior surface" like the "dielectric liner" does, as recited in claim 10. Even if combined with the "dielectric fill material 385" of PAUL (which the Office Action points to as disclosing the "dielectric fill" from claim 10), there is no component in PAUL that fully covers the "dielectric liner." However, Paul et al. (US 2020/0111798) disclose the gate cut (305A and 385 in Fig. 3B) includes a dielectric liner 305A (Fig. 3B, paragraph 0056) lining a bottom (bottom of 305Ain Fig. 3B) and sides (left side of 305A contacting 315 and right side of 305A contacting 392.2 in Fig. 3B) of the gate cut (305A and 385 in Fig. 3B) on an exterior surface (left side surface of 305A contacting 306 in Fig. 3B) and lining a dielectric fill layer 385 (Fig. 3B, paragraph 0060) on an interior surface (interface between 385 and 305A in Fig. 3B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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