DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0034] on page 8 discloses “and the second capping layer CL2 that are patterned may have each have a width same as that of the second spacer 102S.”; this phrase should be corrected.
Paragraph [0037] on page 9 recites “The patterned second mask layer ML2 may be removed to for an opening between the third spacers 103S”; this should be written as “The patterned second mask layer ML2 may be removed to form an opening between the third spacers 103S.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “about” in claims 9 and 17 is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Claim 9 recites “wherein a width of the patterned second mask layer is in a range of about 60 Å to about 70 Å.” The use of the word “about” in claim 9 causes uncertainty to the exact width boundaries of the patterned second mask layer and there is no explanation of the tolerances in the specification.
Claim 17 recites “wherein a width of each of the plurality of second spacers is in a range of about 190 Å to about 230 Å.” The use of the word “about” in claim 17 causes uncertainty to the exact width boundaries of each of the plurality of second spacers and there is no explanation of the tolerances in the specification.
Allowable Subject Matter
Claims 1, 10, and 19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, the closest prior art Yun (US20050272250A1) discloses a method of fabricating a semiconductor device (method of manufacturing a semiconductor memory device [0029]).
Yun discloses: the method comprising:
forming an active pattern on a substrate (forming an isolation region 310 to define active regions 320 on semiconductor substrate 300), FIG. 10, [0030].
forming a plurality of first spacers on sidewalls of the patterned mask layer (forming bit line spacer layers 370 on sidewalls of the bit line stacks 360, each bit line stack including the mask layer 363), FIG. 20, [0032].
using the patterned base mask as a mask to etch a trench in the active pattern (performing etching process using mask layer patterns and gate spacer layers as etching masks to expose portions of active regions 320 of the substrate 300), FIG. 17, [0031];
and forming a gate structure (forming gate stacks 350 on substrate 300), FIG. 17,
[0030].
Yun does not disclose “sequentially forming on the substrate a base mask, a first mask layer, a first capping layer, a second mask layer, a second capping layer, a third mask layer, a third capping layer, a fourth mask layer, and a fourth capping layer; patterning the fourth mask layer and the fourth capping layer, the patterning the fourth mask layer providing a patterned fourth mask layer; using the first spacers as a mask to pattern the third mask layer and the third capping layer such that a patterned third mask layer and a patterned third capping layer are provided; forming a plurality of second spacers on sidewalls of the patterned third mask layer; using the second spacers as a mask to pattern the second mask layer and the second capping layer such that a patterned second mask layer and a patterned second capping layer are provided; forming a plurality of third spacers on sidewalls of the patterned second mask layer; using the third spacers as a mask to pattern the first mask layer and the first capping layer such that a patterned first mask layer and a patterned first capping layer are provided; using the patterned first mask layer and the patterned first capping layer as a mask to pattern the base mask such that a patterned base mask is provided; and forming a gate structure in the trench, wherein the forming the plurality of third spacers includes forming a spacer layer to completely fill a space between the sidewalls of the patterned second mask layer“ in combination with the remaining features.
Claims 2-8 are allowed by virtue of their dependency on claim 1.
Claim 9 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph set forth in the Office action.
Regarding Claim 10, the closest prior art Yun (US20050272250A1) discloses a method of fabricating a semiconductor device (method of manufacturing a semiconductor memory device [0029]).
Yun discloses: the method comprising:
forming an active pattern on a substrate (forming an isolation region 310 to define active regions 320 on semiconductor substrate 300), FIG. 10, [0030].
forming a plurality of first spacers on sidewalls of the third mask layer (forming bit line spacer layers 370 on sidewalls of the bit line stacks 360, each bit line stack including the mask layer 363), FIG. 20, [0032].
Yun does not disclose “sequentially forming on the substrate a base mask, a first mask layer, a first capping layer, a second mask layer, a second capping layer, a third mask layer, and a third capping layer; patterning the third mask layer and the third capping layer; using the first spacers as a mask to pattern the second mask layer and the second capping layer such that a patterned second mask layer and a patterned second capping layer are provided; forming a plurality of second spacers on sidewalls of the patterned second mask layer; using the second spacers as a mask to pattern the first mask layer and the first capping layer such that a patterned first mask layer and a patterned first capping layer are provided; using the patterned first mask layer and the patterned first capping layer as a mask to pattern the base mask such that a patterned base mask is provided; and forming a trench in the active pattern using the patterned base mask as a mask, wherein the forming the plurality of second spacers includes forming a spacer layer on the patterned second mask layer and the patterned second capping layer, and etching the spacer layer, the spacer layer has a first curved surface and a second curved surface that are in contact with each other, and a contact point between the first curved surface and the second curved surface is between patterns of the patterned second mask layer.” in combination with the remaining features.
Claims 11-16, and 18 are allowed by virtue of their dependency on claim 10.
Claim 17 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph set forth in the Office action.
Regarding Claim 19, the closest prior art Yun (US20050272250A1) discloses a method of fabricating a semiconductor device (method of manufacturing a semiconductor memory device [0029]).
Yun discloses: the method comprising:
forming an active pattern on a substrate (forming an isolation region 310 to define active regions 320 on semiconductor substrate 300), FIG. 10, [0030].
forming a plurality of first spacers on sidewalls of the patterned fourth mask layer and sidewalls of the patterned fourth capping layer (forming bit line spacer layers 370 on sidewalls of the bit line stacks 360, each bit line stack including the mask layer 363), FIG. 20, [0032].
depositing a spacer layer (capping spacer layer 334 is formed on the remaining third insulating layer 333′, the bit line stacks 360, and the bit line spacer layers 370), FIG. 25, [0038].
removing an upper portion of the spacer layer (dry etching process removes portions of capping spacer layer), FIG. 26, [0039].
Yun does not disclose “sequentially forming on the substrate a base mask, a first mask layer, a first capping layer, a second mask layer, a second capping layer, a third mask layer, a third capping layer, a fourth mask layer, and a fourth capping layer; patterning the fourth mask layer and the fourth capping layer, the patterning the fourth mask layer and the fourth capping layer providing a patterned fourth mask layer and a patterned fourth capping layer; removing the patterned fourth mask layer and the patterned fourth capping layer; using the first spacers as a mask to pattern the third mask layer and the third capping layer such that a patterned third mask layer and a patterned third capping layer are provided; forming a plurality of second spacers on sidewalls of the patterned third mask layer and sidewalls of the patterned third capping layer; removing the patterned third mask layer and the patterned third capping layer; using the second spacers as a mask to pattern the second mask layer and the second capping layer such that a patterned second mask layer and a patterned second capping layer are provided; depositing a spacer layer that completely fills spaces between patterns of the patterned second mask layer and fills spaces between patterns of the patterned second capping layer; removing an upper portion of the spacer layer to form a plurality of third spacers; removing the patterned second mask layer and the patterned second capping layer; using the third spacers as a mask to pattern the first mask layer and the first capping layer such that a patterned first mask layer and a patterned first capping layer are provided; using the patterned first mask layer and the patterned first capping layer to pattern the base mask such that a patterned base mask is provided; and using the patterned base mask to form a trench in the active pattern.” in combination with the remaining features.
Claim 20 is allowed by virtue of its dependency on claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Krishna Palaniswamy whose telephone number is
(571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM
EST. Examiner interviews are available via telephone, in-person, and video
conferencing using a USPTO supplied web-based collaboration tool. To schedule an
interview, applicant is encouraged to use the USPTO Automated Interview Request
(AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number
for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is
available to registered users. To file and manage patent submissions in Patent Center,
visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent -
center for more information about Patent Center and ttps://www.uspto.gov/patents/docx
for information about filing in DOCX format. For additional questions, contact the
Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN
USA OR CANADA) or 571-272-1000.
/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights