DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 2, the claim recites “about 1.005 times to about 1.1 times”, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim is intended to limit the thickness ratio to a particular range of values, such as +/-5%, +/-10%, or some other range. This renders the scope of the claim indefinite. For the purpose of compact prosecution, the Examiner has interpreted “about 1.005 times to about 1.1 times” to mean “1.005 times to 1.1 times”.
Regarding claim 3, the claim recites the term “substantially the same thickness”, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim is intended to limit a difference in thickness to a particular range of values, such as +/-5%, +/-10%, or some other range. This renders the scope of the claim indefinite. For the purpose of compact prosecution, the Examiner has interpreted “substantially the same thickness” to mean “the same thickness”.
Regarding claim 19, the claim recites the limitation “the input/output pad” in line 8 of the claim, however there is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “an input/output pad of the set of input/output pads”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter.
Regarding claim 20, the claim recites the term “substantially the same thickness”, which does not adequately define the metes and bounds of the claim, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of ordinary skill in the art would only conclude that certain exemplary embodiments qualify, but without a definite criterion by which to ascertain whether any non-disclosed embodiments so qualifies. For example, it is unclear if the claim is intended to limit a difference in thickness to a particular range of values, such as +/-5%, +/-10%, or some other range. This renders the scope of the claim indefinite. For the purpose of compact prosecution, the Examiner has interpreted “substantially the same thickness” to mean “the same thickness”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 9-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Baraskar et al (US 20200388626 A1, hereafter Baraskar) in view of Shim et al (US 20100078701 A1, hereafter Shim) and Wang et al (US 20200411544 A1, hereafter Wang).
Regarding claim 1, Baraskar teaches: A semiconductor device (Baraskar ¶0241, 0350, figs 1, 21A, 41), comprising:
a peripheral circuit region (Baraskar 700) including a first substrate (Baraskar 8/9, ¶0104)(Baraskar fig 1, 41), circuit devices (Baraskar 710, ¶0106, 0241) on the first substrate (Baraskar fig 1, 41), and a first interconnection structure (Baraskar 780, ¶0243-0245) electrically connected to the circuit devices (Baraskar ¶0243, fig 41); and
a memory cell region (Baraskar 100) that overlaps the peripheral circuit region (Baraskar ¶0256, fig 41),
wherein the memory cell region includes:
a second substrate (Baraskar 110, 114, ¶0248-0252);
a stack of gate electrodes (Baraskar 46, 146, 246, ¶0206, 0338) and interlayer insulating layers (Baraskar 32, 132, 232, ¶0111, 0259) alternately stacked in a vertical direction perpendicular to an upper surface of the second substrate (Baraskar ¶0110, 0231, 0262, 0290, fig 41); and
a channel structure (Baraskar 55, 60, ¶0308) that extends through the stack and includes a channel layer (Baraskar 60)(Baraskar ¶0157, 0231, fig 5H),
wherein the gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, third gate electrodes on the second gate electrodes, fourth gate electrodes on the third gate electrodes, and fifth gate electrodes on the fourth gate electrodes (Baraskar 46, 146, 246, fig 41, ¶0203, 0338, plurality of layers at different vertical levels),
wherein the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, third interlayer insulating layers on the second interlayer insulating layers, fourth interlayer insulating layers on the third interlayer insulating layers, and fifth interlayer insulating layers on the fourth interlayer insulating layers (Baraskar 32, 132, 232, fig 41, ¶0110-0112, 0259-0262, 0338, plurality of layers at different vertical levels).
Baraskar does not teach: wherein each of the fourth gate electrodes has a first thickness that is greater than a second thickness of each of the third gate electrodes, and
wherein each of the second interlayer insulating layers has a third thickness that is greater than a fourth thickness of each of the third interlayer insulating layers.
Shim, in the same field of endeavor of semiconductor device manufacturing, teaches: a stack of gate electrodes (Shim HP, 41-44, fig 3, 4, 8B, ¶0046, 0051) and interlayer insulating layers (Shim 31-35, fig 3, 4, 8B, ¶0046) alternately stacked in a vertical direction perpendicular to an upper surface of a substrate (Shim 10)(Shim fig 3, 4, 8B),
a channel structure that extends through the stack and includes a channel layer (Shim VP, 60)(Shim fig 3, 4, 8B, ¶0050-0051, 0069),
wherein the gate electrodes include second gate electrodes (Shim Group I, ¶0083) on the first gate electrodes (Shim fig 24, ¶0083), third gate electrodes (Shim Group II, ¶0083) on the second gate electrodes (Shim fig 24, ¶0083), and fourth gate electrodes (Shim Group III, ¶0083) on the third gate electrodes (Shim fig 24, ¶0083),
wherein each of the fourth gate electrodes has a first thickness (Shim t3, fig 24, ¶0083) that is greater than a second thickness (Shim t2, fig 24, ¶0083) of each of the third gate electrodes (Shim, fig 24, ¶0083).
Shim further teaches: groups of gate electrodes with the same thickness having different thicknesses than other groups (Shim fig 24, ¶0083).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate electrodes of Baraskar to have a thickness that increases with distance from the substrate, and such that “each of the fourth gate electrodes has a first thickness that is greater than a second thickness of each of the third gate electrodes”, as taught by Shim, in order to compensate for reduced channel width due to tapering, thereby reducing current drive variation among memory cells at different vertical positions (Shim ¶0045, 0052, 0055-0057), and further to group gate electrodes together in a vertical region in order reduce manufacturing complexing by keeping a constant thickness when channel width changes are minimal (Shim ¶0083).
Baraskar in view of Shim does not teach: wherein each of the second interlayer insulating layers has a third thickness that is greater than a fourth thickness of each of the third interlayer insulating layers.
Wang, in the same field of endeavor of semiconductor device manufacturing, teaches:
a stack of gate electrodes (Wang 121, ¶0045, 0057) and interlayer insulating layers (Wang 112, ¶0049, 0078) alternately stacked in a vertical direction perpendicular to an upper surface of a substrate (Wang 13)(Wang fig 11); and
a channel structure (Wang 14) that extends through the stack (Wang fig 11), and
adjusting a thickness of interlayer insulating layers given a width of the channel structure within a region (Wang ¶0007, 0044, 0051, 0084)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust a thickness of the interlayer insulating layers of Baraskar in view of Shim to distance from the substrate, corresponding inversely to the gate electrodes of Baraskar in view of Shim, and such that “each of the second interlayer insulating layers has a third thickness that is greater than a fourth thickness of each of the third interlayer insulating layers”, in order to reduce threshold voltage distribution width, and/or improve program/erase speed cell uniformity (Wang ¶0036-0037, 0057).
Regarding claim 4, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein each of the first interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to first gate electrodes) has a fifth thickness that is greater than the fourth thickness of each of the third interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to fourth gate electrodes)(Baraskar in view of Shim as modified by Wang has interlayer insulating layers at a position closer to the substrate having a greater thickness).
Regarding claim 5, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein each of the fifth gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a fifth group thickness) has a sixth thickness that is greater than the second thickness of each of the third gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a third group thickness, similar to Shim Group II)(Baraskar as modified by Shim has gate electrodes at a position further from the substrate having a greater thickness).
Regarding claim 6, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein each of the first interlayer insulating layers ((Baraskar 32, 132, 232 as modified by Wang 112, corresponding to first gate electrodes) has a fifth thickness that is greater than the fourth thickness of each of the third interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to third gate electrodes)(Baraskar in view of Shim as modified by Wang has interlayer insulating layers at a position closer to the substrate having a greater thickness), and wherein each of the fifth gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a fifth group thickness) has a sixth thickness that is greater than the second thickness of each of the third gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a third group thickness, similar to Shim Group II)(Baraskar as modified by Shim has gate electrodes at a position further from the substrate having a greater thickness).
Regarding claim 9, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein the gate electrodes (Baraskar 46, 146, 246 as modified by Shim) further include a string selection gate electrode (Baraskar 246, ¶0125, 0341, “drain select gate electrodes”, similar to Shim USL, ¶0068, 0084) on the fifth gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a fifth group thickness)(Shim fig 24, Baraskar fig 41), and wherein the string selection gate electrode has a thickness that is greater than the second thickness of each of the third gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a third group thickness, similar to Shim Group II)(Shim ¶0068, 0084, fig 25).
Regarding claim 10, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein the gate electrodes (Baraskar 46, 146, 246 as modified by Shim) further include a ground selection gate electrode (Baraskar 118, ¶0132, 0252, 0268, similar to Shim LSL, ¶0068, 0084) below the first gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a first group thickness)(Shim fig 24, Baraskar fig 21C, 41), and wherein the ground selection gate electrode has a thickness that is greater than the second thickness of each of the third gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a third group thickness, similar to Shim Group II)(Shim ¶0068, 0084, fig 25).
Regarding claim 11, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein the gate electrodes (Baraskar 46, 146, 246 as modified by Shim) further include an erase gate electrode (Baraskar 246, ¶0125, 0341, similar to Shim USL, ¶0068, 0084, at least capable of being use in an erase operation) on the fifth gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a fifth group thickness)(Shim fig 24, Baraskar fig 41), and wherein the erase gate electrode has a thickness that is greater than the second thickness of each of the third gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a third group thickness, similar to Shim Group II)(Shim ¶0068, 0084, fig 25).
Regarding claim 12, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein the memory cell region (Baraskar 100) further includes first to fifth gate contacts (Baraskar 86, ¶0347) that are electrically connected to the first to fifth gate electrodes (Baraskar 46, 146, 246 as modified by Shim), respectively (Baraskar fig 41, ¶0347).
Regarding claim 15, Baraskar in view of Shim and Wang teaches: The semiconductor device of claim 1, wherein the first gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a first group thickness) and the first interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to first gate electrodes) are repeatedly and alternately stacked in the vertical direction (Baraskar fig 41, similar to Shim fig 24 and Wang fig 11),
wherein the second gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a second group thickness, similar to Shim Group I) and the second interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to second gate electrodes) are repeatedly and alternately stacked in the vertical direction (Baraskar fig 41, similar to Shim fig 24 and Wang fig 11),
wherein the third gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a third group thickness, similar to Shim Group II) and the third interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to third gate electrodes) are repeatedly and alternately stacked in the vertical direction (Baraskar fig 41, similar to Shim fig 24 and Wang fig 11),
wherein the fourth gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a fourth group thickness, similar to Shim Group III) and the fourth interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to fourth gate electrodes) are repeatedly and alternately stacked in the vertical direction (Baraskar fig 41, similar to Shim fig 24 and Wang fig 11), and
wherein the fifth gate electrodes (Baraskar 46, 146, 246 as modified by Shim to have a fifth group thickness) and the fifth interlayer insulating layers (Baraskar 32, 132, 232 as modified by Wang 112, corresponding to fifth gate electrodes) are repeatedly and alternately stacked in the vertical direction (Baraskar fig 41, similar to Shim fig 24 and Wang fig 11)(Baraskar ¶0259-0262, wherein each group contains at least one gate electrode and at least on interlayer insulating layer, stacked vertically and alternatively at least once in a vertical direction).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Shim et al (US 20100078701 A1, hereafter Shim).
Regarding claim 16, Shim teaches: A semiconductor device (Shim ¶0002-0006, fig 8A, 8B, 24), comprising:
a stack structure (Shim ¶0046, 0073, fig 11) including gate electrodes (Shim HP, 41-44, 201-206, fig 3, 4, 8B, ¶0046, 0051) and interlayer insulating layers (Shim 31-35, 211-216, fig 3, 4, 8B, ¶0046) repeatedly and alternately stacked in a vertical direction (Shim fig 3, 4, 8B); and
a channel structure (Shim VP, 60, ¶0050-0051) that extends through the stack structure (Shim fig 3, 4, 8B, ¶0050-0051, 0069),
wherein the gate electrodes include first gate electrodes (Shim Group I, ¶0083), second gate electrodes (Shim Group II, ¶0083) on the first gate electrodes (Shim fig 24, ¶0083), and third gate electrodes (Shim Group III, ¶0083) on the second gate electrodes (Shim fig 24, ¶0083),
wherein each of the first gate electrodes has a first thickness (Shim t1, fig 24, ¶0055, 0083),
wherein each of the second gate electrodes has a second thickness (Shim t2, fig 24, ¶0055, 0083) that is greater than the first thickness (Shim, fig 8B, 24, ¶0067, 0083), and
wherein each of the third gate electrodes has a third thickness (Shim t3, fig 24, ¶0083).
Shim does not explicitly teach: wherein each of the third gate electrodes has a third thickness that is smaller than the second thickness.
Shim further teaches: a channel structures having different profiles (Shim ¶0064, barrel-shaped having a wider middle than either end).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust the thicknesses of the second or third gate electrodes, such that “the third gate electrodes has a third thickness that is smaller than the second thickness” in order to compensate for different channel geometries while maintaining reduced electrical variations (Shim ¶0051-0052, 0064).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Baraskar et al (US 20200388626 A1, hereafter Baraskar) in view of Shim et al (US 20100078701 A1, hereafter Shim), Wang et al (US 20200411544 A1, hereafter Wang) and Yun et al (US 20130032875 A1, hereafter Yun).
Regarding claim 19, Baraskar teaches: An electronic system, comprising: a semiconductor device (Baraskar ¶0241, 0350, figs 1, 21A, 41), wherein the semiconductor device includes:
a peripheral circuit region (Baraskar 700) including a first substrate (Baraskar 8/9, ¶0104)(Baraskar fig 1, 41), circuit devices (Baraskar 710, ¶0106, 0241) on the first substrate (Baraskar fig 1, 41), and a first interconnection structure (Baraskar 780, ¶0243-0245) electrically connected to the circuit devices (Baraskar ¶0243, fig 41); and
a memory cell region (Baraskar 100) that overlaps the peripheral circuit region (Baraskar ¶0256, fig 41);
a set of input/output pads (Baraskar 788) electrically connected to the circuit devices (Baraskar fig 41); and
wherein the memory cell region includes:
a second substrate (Baraskar 110, 114, ¶0248-0252);
gate electrodes (Baraskar 46, 146, 246, ¶0206, 0338) stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate (Baraskar fig 41);
interlayer insulating layers (Baraskar 32, 132, 232, ¶0111, 0259) alternately stacked with the gate electrodes (Baraskar ¶0110, 0231, 0262, 0290, fig 41); and
a channel structure (Baraskar 55, 60, ¶0308) that extends through the gate electrodes (Baraskar fig 5H, 41), the channel structure extending perpendicularly to the second substrate and including a channel layer (Baraskar 60)(Baraskar ¶0157, 0231, fig 5H),
wherein the gate electrodes include first gate electrodes, second gate electrodes on the first gate electrodes, third gate electrodes on the second gate electrodes, fourth gate electrodes on the third gate electrodes, and fifth gate electrodes on the fourth gate electrodes (Baraskar 46, 146, 246, fig 41, ¶0203, 0338, plurality of layers at different vertical levels),
wherein the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, third interlayer insulating layers on the second interlayer insulating layers, fourth interlayer insulating layers on the third interlayer insulating layers, and fifth interlayer insulating layers on the fourth interlayer insulating layers (Baraskar 32, 132, 232, fig 41, ¶0110-0112, 0259-0262, 0338, plurality of layers at different vertical levels).
Baraskar does not teach: a controller electrically connected to the semiconductor device through the input/output pad (as best understood to mean “an input/output pad of the set of input/output pads”) and controlling the semiconductor device,
wherein each of the fourth gate electrodes has a first thickness that is greater than a second thickness of each of the third gate electrodes, and
wherein each of the second interlayer insulating layers has a third thickness that is greater than a fourth thickness of each of the third interlayer insulating layers.
Shim, in the same field of endeavor of semiconductor device manufacturing, teaches: a stack of gate electrodes (Shim HP, 41-44, fig 3, 4, 8B, ¶0046, 0051) and interlayer insulating layers (Shim 31-35, fig 3, 4, 8B, ¶0046) alternately stacked in a vertical direction perpendicular to an upper surface of a substrate (Shim 10)(Shim fig 3, 4, 8B),
a channel structure that extends through the stack and includes a channel layer (Shim VP, 60)(Shim fig 3, 4, 8B, ¶0050-0051, 0069),
wherein the gate electrodes include first gate electrodes (Shim LSL, ¶0083), second gate electrodes (Shim Group I, ¶0083) on the first gate electrodes (Shim fig 24, ¶0083), third gate electrodes (Shim Group II, ¶0083) on the second gate electrodes (Shim fig 24, ¶0083), fourth gate electrodes (Shim Group III, ¶0083) on the third gate electrodes (Shim fig 24, ¶0083), and fifth gate electrodes (Shim USL, ¶0083) on the fourth gate electrodes (Shim fig 24, ¶0083),
wherein each of the fourth gate electrodes has a first thickness (Shim t3, fig 24, ¶0083) that is greater than a second thickness (Shim t2, fig 24, ¶0083) of each of the third gate electrodes (Shim, fig 24, ¶0083).
Shim further teaches: groups of gate electrodes with the same thickness having different thicknesses than other groups (Shim fig 24, ¶0083).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the gate electrodes of Baraskar to have a thickness that increases with distance from the substrate, and such that “each of the fourth gate electrodes has a first thickness that is greater than a second thickness of each of the third gate electrodes”, as taught by Shim, in order to compensate for reduced channel width due to tapering, thereby reducing current drive variation among memory cells at different vertical positions (Shim ¶0045, 0052, 0055-0057), and further to group gate electrodes together in a vertical region in order reduce manufacturing complexing by keeping a constant thickness when channel width changes are minimal (Shim ¶0083).
Baraskar in view of Shim does not teach: a controller electrically connected to the semiconductor device through the input/output pad (as best understood to mean “an input/output pad of the set of input/output pads”) and controlling the semiconductor device,
wherein each of the second interlayer insulating layers has a third thickness that is greater than a fourth thickness of each of the third interlayer insulating layers.
Wang, in the same field of endeavor of semiconductor device manufacturing, teaches:
a stack of gate electrodes (Wang 121, ¶0045, 0057) and interlayer insulating layers (Wang 112, ¶0049, 0078) alternately stacked in a vertical direction perpendicular to an upper surface of a substrate (Wang 13)(Wang fig 11); and
a channel structure (Wang 14) that extends through the stack (Wang fig 11), and
adjusting a thickness of interlayer insulating layers given a width of the channel structure within a region (Wang ¶0007, 0044, 0051, 0084)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to adjust a thickness of the interlayer insulating layers of Baraskar in view of Shim to distance from the substrate, corresponding inversely to the gate electrodes of Baraskar in view of Shim, and such that “each of the second interlayer insulating layers has a third thickness that is greater than a fourth thickness of each of the third interlayer insulating layers”, in order to reduce threshold voltage distribution width, and/or improve program/erase speed cell uniformity (Wang ¶0036-0037, 0057).
Baraskar in view of Shim and Wang does not teach: a controller electrically connected to the semiconductor device through the input/output pad (as best understood to mean “an input/output pad of the set of input/output pads”) and controlling the semiconductor device.
Yun, in the same field of endeavor of semiconductor device manufacturing, teaches: a controller electrically connected to the semiconductor device through an input/output pad and controlling the semiconductor device (Yun fig 38A).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Baraskar in view of Shim and Wang to include the controller of Wang such that it “connected to the semiconductor device through the input/output pad and controlling the semiconductor device”, in order to enable the semiconductor device to be used in a data storage system by providing communication and/or device management (Yun ¶0150).
Allowable Subject Matter
Claims 7, 8, 13, 14, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 2, 3, and 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 17, it is allowable, notwithstanding the above objection, primarily because the prior arts of record, singly or in combination, neither anticipates nor render obvious the following limitations when taken in combination with all other limitations:
wherein each of the third interlayer insulating layers has a fourth thickness, wherein each of the second interlayer insulating layers has a fifth thickness that is greater than the fourth thickness, and
wherein each of the first interlayer insulating layers has a sixth thickness greater than the fourth thickness. (Applicant ¶0043).
Shim et al (US 20100078701 A1, hereafter Shim) teaches: The semiconductor device of claim 16, wherein the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, and third interlayer insulating layers on the second interlayer insulating layers (Shim 31-35, 210, 211-216, fig 3, 4, 8B, 11, ¶0046).
Wang et al (US 20200411544 A1, hereafter Wang) teaches: A semiconductor device (Wang 2800, ¶0038, fig 28), wherein the interlayer insulating layers include first interlayer insulating layers, second interlayer insulating layers on the first interlayer insulating layers, and third interlayer insulating layers on the second interlayer insulating layers (Wang 112, ¶0084-0086, 00991-0093),
wherein each of the third interlayer insulating layers has a fourth thickness (Wang ¶0082, 0089, fig 28), wherein each of the second interlayer insulating layers has a fifth thickness (Wang ¶0084-0086, fig 28), and
wherein each of the first interlayer insulating layers has a sixth thickness (Wang ¶0082, 0089, fig 28).
Wang further teaches: ILD thickness is inversely proportional to channel width (Wang ¶0006, 0004, 0009, 0101).
Therefore, Shim in view of Wang in combination disclose some of the features of the claimed invention, but there is no motivation/teaching and do not render obvious to combine and/or modify Shim, Wang, or any other prior arts of record so that all of limitations of claim 17 as a whole can be met.
Regarding claim 18, the dependent claim is allowable for its dependency to claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al (US 20130193395 A1) is cited as an example of an analogous device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/Mounir S Amer/Primary Examiner, Art Unit 2818