DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/21/2023 considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “bottom top surface of the substrate” in line 10. There is a grammatical and idiomatic errors.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 12-14 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2021/0358875).
Regarding claim 1, Lee teaches a semiconductor package in fig. 1, comprising:
a substrate (130);
a first semiconductor chip (140) on the substrate, wherein the first semiconductor chip (140) includes a through via (145) in the first semiconductor chip (140) and a plurality of first bonding pads (BP1) on an upper portion of the first semiconductor chip (refer to an upper surface of 140);
a second semiconductor chip (150) on the first semiconductor chip (140), wherein the second semiconductor chip (150) includes a plurality of second bonding pads (BP2) on a lower portion of the second semiconductor chip (refer to a lower surface of 150); and
a conductive post (CP) between a top surface of the substrate (130) and a bottom surface of the second semiconductor chip (refer to the lower surface of 150) and laterally spaced apart from the first semiconductor chip (NOTE: CP is placed on lateral sides of 140), wherein the first bonding pads (BP1) are in contact with the second bonding pads (BP2), and wherein a width in a first direction parallel to a plane defined by a bottom surface of the substrate of the second semiconductor chip (refer to W2 in the notation below) is greater than a width in the first direction of the first semiconductor chip (refer to W1 in the notation below).
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Regarding claim 2, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Lee teaches the first semiconductor chip further includes a first passivation layer (BO1) on the upper portion of the first semiconductor chip (refer to an upper surface of 140), the first passivation layer (BO1) extending along lateral surfaces of the first bonding pads (BP1), the second semiconductor chip (150) further includes a second passivation layer (BO2) on the lower portion of the second semiconductor chip (refer to a lower surface of 150), the second passivation layer(BO2) extending along lateral surfaces of the second bonding pads (BP2), and a top surface of the first passivation layer (BO1) is in contact with a bottom surface of the second passivation layer (BO2).
Regarding claim 3, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Lee teaches a third bonding pad (BP3) coupled to the conductive post (CP) and spaced apart in the first direction from the first semiconductor chip (refer to left to right direction), wherein the second semiconductor chip (150) further includes a fourth bonding pad (BP4) on the lower portion of the second semiconductor chip (refer to a lower surface of 150), the fourth bonding pad (BP4) vertically overlapping the conductive post (CP) in a second direction perpendicular to the plane defined by the bottom surface of the substrate, and wherein the third bonding pad and the fourth bonding pad are in contact with each other (see fig. 1).
Regarding claim 4, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Lee teaches a bump structure (110) below the first semiconductor chip (140) where the bottom surface of the substrate provides a base reference plane, wherein the bump structure includes:
a bump pad (120) below the conductive post (CP) and below the through via (145) where the bottom surface of the substrate provides the base reference plane;
a barrier pattern (131V) in contact with a bottom surface of the bump pad; and
a bonding pattern (131L) and a solder bump (110) that are sequentially provided in a downward direction below the barrier pattern where bottom top surface of the substrate provides the base reference plane (see fig. 1).
Regarding claim 6, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Lee teaches the through via (146) has a first width in the first direction, the conductive post (CP) has a second width in the first direction, and the second width is greater than the first width (see fig. 1).
Regarding claim 12, Lee teaches a semiconductor package in fig. 9, comprising:
a substrate (130);
a first semiconductor chip (140) on the substrate (130) and including a through via (145) in the first semiconductor chip, the first semiconductor chip having a first width in a first direction (refer to W1);
a second semiconductor chip (150) on the first semiconductor chip (140), the second semiconductor chip having a second width in the first direction (refer to W2), wherein the second width is greater than the first width (see notation below);
a first molding layer (MD1) that surrounds the first semiconductor chip (140) in a plan view (see fig. 9);
a second molding layer (MD2) that surrounds the second semiconductor chip (150) in the plan view, wherein the second width is greater than the first width, and wherein a portion of a top surface of the first molding layer is in contact with an entirety of a bottom surface of the second molding layer.
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Regarding claim 13, Lee teaches all the limitation of the claimed invention for the same reasons as set forth above. Besides, Lee teaches the top surface of the first molding layer (MD1) is coplanar with a top surface of the first semiconductor chip, and the bottom surface of the second molding layer (MD2) is coplanar with a bottom surface of the second semiconductor chip (see fig. 9).
Regarding claim 14, Lee teaches all the limitation of the claimed invention for the same reasons as set forth above. Besides, Lee teaches a sidewall of the first molding layer (MD1) is linearly aligned with a sidewall of the second molding layer (MD2) (see fig. 9).
Regarding claim 16, Lee teaches all the limitation of the claimed invention for the same reasons as set forth above. Besides, Lee teaches a conductive post (CP) on the substrate (130) and spaced apart in the first direction from the first semiconductor chip, the first direction being parallel to a bottom surface of the substrate, wherein the conductive post (CP) vertically overlaps a portion of the second semiconductor chip (150) in a second direction perpendicular to the bottom surface of the substrate.
Regarding claim 17, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Lee teaches a bump structure (110) below the first semiconductor chip (140) where the bottom surface of the substrate provides a base reference plane, wherein the bump structure includes:
a bump pad (120) below the conductive post (CP) and below the through via (145) where the bottom surface of the substrate provides the base reference plane;
a barrier pattern (131V) in contact with a bottom surface of the bump pad; and
a bonding pattern (131L) and a solder bump (110) that are sequentially provided in a downward direction below the barrier pattern where bottom surface of the substrate provides the base reference plane (see fig. 9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210358875) as applied to claim 1 above, and further in view of Lu (US 20210118811).
Regarding claim 5, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above except for a passive element mounted on a bottom surface of the substrate, wherein the conductive post vertically overlaps at least a portion of the passive element in a second direction perpendicular to the plane defined by the bottom surface of the substrate.
Lu teaches the same field of an endeavor wherein a passive element (292) mounted on a bottom surface of the substrate (270), wherein the conductive post vertically overlaps at least a portion of the passive element in a second direction perpendicular to the plane defined by the bottom surface of the substrate (see notation below).
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Thus it would have been obvious to one having ordinary skills in the art before the invention was made to include a passive element mounted on a bottom surface of the substrate, wherein the conductive post vertically overlaps at least a portion of the passive element in a second direction perpendicular to the plane defined by the bottom surface of the substrate as taught by Lu in the teaching of Lee so that it allows the compact and efficient placement of the components within the package, reduce the overall footprint device.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210358875) as applied to claim 1 above, and further in view of Chen (US 2020/0343223).
Regarding claim 7, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above except for a first molding layer on a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and a sidewall of the conductive post, wherein a top surface of the first molding layer is coplanar with a top surface of the second semiconductor chip.
Chen teaches the same field of an endeavor wherein a first molding layer (112’) on a sidewall of the first semiconductor chip (204), a sidewall of the second semiconductor chip (202), and a sidewall of the conductive post (110) (as labelled in fig. 1F), wherein a top surface of the first molding layer is coplanar with a top surface of the second semiconductor chip (see fig. 5).
Thus it would have been obvious to one having ordinary skills in the art before the invention was made to include a first molding layer on a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and a sidewall of the conductive post, wherein a top surface of the first molding layer is coplanar with a top surface of the second semiconductor chip as taught by Chen in the teaching of Lee so that it provides a protection to the first semiconductor chip, the second semiconductor chip, and the conductive post from external environment.
Regarding claim 8, Lee and Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 5 of Chen teaches a connection structure (306) on the substrate (RDL2) and spaced apart in the first direction from the first molding layer (112’) ; and a second molding layer (308’) on a sidewall of the connection structure (306) and a sidewall of the first molding layer (112’).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210358875) as applied to claim 1 above, and further in view of Chen (US 2020/0343223).
Regarding claim 15, Lee teaches all the limitations of the claimed invention for the same reasons as set forth above except for a third molding layer on a sidewall of the first molding layer and on a sidewall of the second molding layer, wherein the third molding layer is further on at least a portion of a bottom surface of the first semiconductor chip and on at least a portion of a top surface of the second semiconductor chip.
Chen teaches the same field of an endeavor wherein a third molding layer (308’) on a sidewall of the first molding layer (refer to molding surrounding die 30) and on a sidewall of the second molding layer (refer to molding surrounding die 200), wherein the third molding layer is further on at least a portion of a bottom surface of the first semiconductor chip and on at least a portion of a top surface of the second semiconductor chip (see fig. 7).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a third molding layer on a sidewall of the first molding layer and on a sidewall of the second molding layer, wherein the third molding layer is further on at least a portion of a bottom surface of the first semiconductor chip and on at least a portion of a top surface of the second semiconductor chip as taught by Chen in the teaching of Lee in order to provide an extra protection surround the first semiconductor die and the second semiconductor die from the external environment.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “a lower redistribution layer below the first semiconductor chip where the bottom surface of the substrate provides the base reference plane, wherein the lower redistribution layer includes: a lower dielectric layer; a plurality of lower redistribution patterns in the lower dielectric layer; and a first lower redistribution pad and a second lower redistribution pad that are coupled to the lower redistribution patterns, wherein the first lower redistribution pad is connected to the through via through one of the lower redistribution patterns, and wherein the second lower redistribution pad is connected to the conductive post through another of the lower redistribution patterns.” Claim 10 includes all the features of claim 9.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “connection substrate including a through hole, wherein the connection substrate includes: a base layer; a vertical structure that extends into the base layer….” in combination of all the limitations of claim 11.
Claim 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “a lower redistribution layer below the first semiconductor chip, wherein the lower redistribution layer includes: a lower dielectric layer; a plurality of lower redistribution patterns in the lower dielectric layer; and a first lower redistribution pad and a second lower redistribution pad that are electrically connected to the lower redistribution patterns, wherein the first lower redistribution pad is coupled to the through via through one of the lower redistribution patterns, and wherein the second lower redistribution pad is coupled to the conductive post through another of the lower redistribution patterns.”
Claims 19-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 19, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a semiconductor package, comprising: “a first redistribution substrate that includes a first dielectric layer, a first seed pattern, and a first conductive pattern on the first seed pattern, wherein the first dielectric layer includes a photo-imageable polymer;..; a connection structure on the top surface of the first redistribution substrate and laterally spaced apart from the conductive post, the first semiconductor chip, and the second semiconductor chip; a first molding layer on the top surface of the first redistribution substrate, wherein the first molding layer is on sidewalls of the connection structure and surrounds the first semiconductor chip and the second semiconductor chip in a plan view; and a second redistribution substrate on the first molding layer and the connection structure, wherein the second redistribution substrate is coupled to the connection structure” in combination of all of the limitations of claim 19. Claims 20-22 include all of the limitations of claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818