DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants’ arguments with respect to claim(s) 1-5, 8-9, 11-13, 17-19 have been considered but are moot because of the new ground. Newly added claims 17-19 and new reference found reference 20240322772.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-13 & 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 11, the recitation of “variably shunting the other one of the load resistor of the TIA or the cascode node of the TIA to reduce the TIA gain by a second amount” is unclear because which the other one of the load resistor is the applicant referring to. It is noted that a single load resistor being defined. It is not clear as to how shunting a load resistor would reduce the TIA gain by first amount and second amount. Further clarification is needed.
Claim 11, the recitation of "the other one of the load resistor”. There is insufficient antecedent basis for this limitation in the claim.
Claims 12-13 & 17 are rejected due to their dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Vera Villarroel et al. (US 2020/0092010 A1, of record), hereinafter Vera Villarroel in view of Singhal et al. (US 20230231522 A1, of record, hereinafter, Singhal) in view of Liu et al. (US 20240322772 A1, hereinafter Liu).
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Fig. 6 of Vera Villarroel
Regarding claim 1
Vera Villarroel discloses in Fig. 6 ( transimpedance amplifier 2 and variable gain amplifier 3 which having similarly arrangement as shown Fig. 2 of the examining application, namely, Front-end TIA and VGA) an apparatus or method comprising:
a transimpedance amplifier “TIA” (2) and a variable gain amplifier (3) form a transimpedance amplifier circuit except for a cascode circuit including a cascode node; and a first tunable element connected to tunably shunt the cascode node to vary a voltage gain of the TIA circuit.
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Fig. 7 of Singhal et al.
Singhal discloses in Fig. 7 adjustable gain amplifier comprising:
Transistors M1, M2 and a cascode circuit including a cascode node (annotated node CASN1, CASN2); and a first tunable element (controllable transistor Madj’) connected to tunably shunt the cascode node to vary a voltage gain of the gain amplifier.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced a generic variable gain amplifier as taught by Vera Villarroel with specific variable gain amplifier as taught by Singhal. Such a modification would have imparted the advantages benefits of improving a wide range of gain attenuation can be achieved with fine resolution without negatively impacting the noise figure and frequency response between the high and low gain modes (Paragraph [0018]).
The combination (Vera Villarroel and Singhal) does not teach a current steering circuit.
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Fig. 2 of Liu et al.
Liu discloses in Fig. 2 an amplifier circuit comprising differential cascode amplification circuit 2 and current-steering structures 3 formed by a group of transistors connected to a cascode node.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of The combination (Vera Villarroel and Singhal) to have the current-steering circuits, as taught by Liu. Such a modification would have imparted the advantageous benefit of improving gain and phase shift fluctuation of the amplification circuit during switching between different gain states is significantly reduced; moreover, the current-steering-based single-stage differential cascode structure in the present disclosure has advantages of simple circuit structure design, small module layout area and low power consumption (Paragraph [0069]), as taught by Liu to the combination (Vera Villarroel and Singhal), thereby suggesting the obviousness of such a modification.
Regarding claims 2 & 3:
The combination (Vera Villarroel and Singhal and Liu) discloses the apparatus of claim 1 wherein the first tunable element comprises a first transistor (controllable transistor Madj’, Fig. 8 of Singhal, see paragraph [0060], transistor Madj’, low impedance, since the transistor Madj’ which having an arrangement similarly to the applicant’s Fig. 4, transistor Vg1, thus the controllable or adjustable transistor Madj’s which is capable of operatable to very impedance of the CAS1, CAS2 node to 6dB or 12dB, see paragraph [0040], gain adjustment transistors, 2dB, 4dB, 10dB and 10-20dB) operable to vary an impedance of the cascode node by at most 6 dB; and (Claim 3) The apparatus of claim 1 wherein the first tunable element comprises a first transistor operable to vary an impedance of the cascode node by at most 12 dB (as above discussion, controllable or adjustable transistor Madj’ which is capable of tuning or vary impedance), it is noted that the applicant used same transistor M1 as shown in Fig. 4 of the applicant to vary multiple different impedance of the cascode node by 6dB or 12dB.
Regarding claim 4:
The combination (Vera Villarroel and Singhal and Liu) discloses the apparatus of claim 1 wherein the first tunable element is a MOS transistor (transistor Madj’, Fig. 7 of Vera Villarroel).
Claims 5 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over the combination (Vera Villarroel and Singhal and Liu) and further in view of Bae et al. (US 20090072904 A1 of record), hereinafter, Bae.
Regarding claim 5:
The combination (Vera Villarroel and Singhal and Liu) discloses the limitations as applied in claim 1 except for a second tunable element connected to shunt a load resistor of the TIA circuit.
Bae discloses in Fig. 3 a variable gain amplifier comprising a transistor M2 being connected between output terminals of transistors Q1 and Q2 and load resistors 302 and 304 being connected being connected to transistors 314, 316 as shown in Fig. 3 of Base.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination circuit of Vera Villarroel in view of Singhal with the teaching transistors M2 and load resistors 302 and 304 as taught by Base. Such a modification would have imparted the advantages benefits of improving gain control linearity (paragraph [0023], a load resistance made up of resistors 302, 304, is provided. In addition, a load resistance is also coupled between the collectors of the pair of transistors 314, 316, the load resistance being a second FET M.sub.2 312 (P-type FET, or PMOS). As FET 312 is turned on, the gain G of the amplifier is decreased. The second gain control is optionally included to enhance the gain control linearity, as well as to extend the range of the gain factor G and to reduce peaking, as described herein).
Regarding claim 8:
The combination (Vera Villarroel and Singhal and Liu and Bae) discloses the apparatus of claim 5, wherein each of the first (control or adjustable transistor Madj’, Singhal) and second tunable (controllable or adjustable or tunable transistor M2 of Base) elements are capable of configuring to reduce the voltage gain of the TIA circuit by no more than 12 dB (see paragraph [0040], gain adjustment transistors, 2dB, 4dB, 10dB and 10-20dB).
Claims 1-4 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 20130236172 A1) in view of Vera Villarroel et al. (US 2020/0092010 A1, of record), hereinafter Vera Villarroel and in view of Singhal et al. (US 20230231522 A1, of record, hereinafter, Singhal) and further in view of Liu et al. (US 20240322772 A1, hereinafter Liu).
Suzuki discloses in Fig. 5 a coherent optical receiver device (100) comprising coherent optical receiver 110 that includes
photoelectrics 112 for detection (i.e. photodetector) being connected to impedance conversion amplifier (TIA) 113 amplifies except for specific limitations as cited in claim 1.
The combination (Vera Villarroel, Singhal and Liu) discloses the limitations of claim 1, see above discussion.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Suzuki to have included the specific limitations as taught by the combination (Vera Villarroel and Singhal and Liu) in order to provide the benefits of cancelling the DC component of the incoming current is a key to increasing the receiver's effectiveness, and therefore increase the channel capacity and improving gain and phase shift fluctuation of the amplification circuit during switching between different gain states is significantly reduced; moreover, the current-steering-based single-stage differential cascode structure in the present disclosure has advantages of simple circuit structure design, small module layout area and low power consumption (Paragraph [0069]).
Accordingly, as an obvious consequence of the combination further discloses a coherent optical receiver (Fig. 5: circuit 200) including a balanced photodetector pair (photodetector 112) connected to the TIA circuit (113), meeting claim 9, see claims 1-4 as discussed above.
Claims 11-13 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over the combination (Vera Villarroel and Singhal and Liu) and further in view of Bae et al. (US 20090072904 A1 of record), hereinafter, Bae).
Insofar regarding claim 11 as best understood
Vera Villarroel discloses in Fig. 6 (transimpedance amplifier 2 and variable gain amplifier 3 which have similar arrangement as shown Fig. 2 of the examining application, namely, Front-end TIA and VGA) an apparatus or method comprising:
a transimpedance amplifier “TIA” (2) and a variable gain amplifier (3) form a transimpedance amplifier circuit except for a cascode circuit including a cascode node; and a first tunable element connected to tunably shunt the cascode node to vary a voltage gain of the TIA circuit.
Singhal discloses in Fig. 7 adjustable gain amplifier comprising:
Transistors M1, M2 and a cascode circuit including a cascode node (annotated node CASN1, CASN2); and a first tunable element (controllable transistor Madj’) connected to tunably shunt the cascode node to vary a voltage gain of the gain amplifier.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced a generic variable gain amplifier as taught by Vera Villarroel with specific variable gain amplifier as taught by Singhal. Such a modification would have imparted the advantages benefits of improving a wide range of gain attenuation can be achieved with fine resolution without negatively impacting the noise figure and frequency response between the high and low gain modes (Paragraph [0018]).
The combination (Vera Villarroel and Singhal) does not teach a current steering circuit.
Liu discloses in Fig. 2 an amplifier circuit comprising differential cascode amplification circuit (transistor 21) and current-steering structures 3 formed by a group of transistors connected to a cascode node.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of The combination (Vera Villarroel and Singhal) to have the current-steering circuits, as taught by Liu. Such a modification would have imparted the advantageous benefit of improving gain and phase shift fluctuation of the amplification circuit during switching between different gain states is significantly reduced; moreover, the current-steering-based single-stage differential cascode structure in the present disclosure has advantages of simple circuit structure design, small module layout area and low power consumption (Paragraph [0069]), as taught by Liu to the combination (Vera Villarroel and Singhal), thereby suggesting the obviousness of such a modification.
The combination (Vera Villarroel and Singhal and Liu) discloses the limitations as applied in claim 1 except for a second tunable element connected to shunt a load resistor of the TIA circuit.
Bae discloses in Fig. 3 a variable gain amplifier comprising a transistor M2 being connected between output terminals of transistors Q1 and Q2 and load resistors 302 and 304 being connected being connected to transistors 314, 316 as shown in Fig. 3 of Base.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination circuit of Vera Villarroel in view of Singhal with the teaching transistors M2 and load resistors 302 and 304 as taught by Base. Such a modification would have imparted the advantages benefits of improving gain control linearity (paragraph [0023], a load resistance made up of resistors 302, 304, is provided. In addition, a load resistance is also coupled between the collectors of the pair of transistors 314, 316, the load resistance being a second FET M.sub.2 312 (P-type FET, or PMOS). As FET 312 is turned on, the gain G of the amplifier is decreased. The second gain control is optionally included to enhance the gain control linearity, as well as to extend the range of the gain factor G and to reduce peaking, as described herein).
Accordingly, as an obvious consequence above, the combination (Vera Villarroel and Singhal, Liu and Bae) further discloses the method comprising variably shunting a load resistor circuit of the TIA to reduce the TIA gain by a first amount; and variably shunting cascode node of the TIA to reduce the TIA gain by a second amount; and (see current steering circuit) steering a tunable fraction of a current flowing through the cascode node away from the load resistor to reduce the TIA gain by a third amount additional to the first and second amounts.
Regarding claim 12:
The combination further discloses wherein the variably shunting either one of the load resistor of the TIA or the cascode node of the TIA decreases the TIA gain by at most 12 dB (Singhal, see paragraph [0040], gain adjustment transistors,10-20dB).
Regarding claim 13:
The combination further discloses wherein the steering (see steering current circuit) a tunable fraction of a current flowing through the cascode node away from the load resistor further decreases the TIA gain by at most 12 dB (Singhal, see paragraph [0040], gain adjustment transistors,10-20dB).
Regarding claim 17:
The combination discloses the limitations as applied in claim 11 except for wherein the variably shunting the cascode node of the TIA decreases an impedance of the cascode node by a factor of 2 or less. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to vary or adjust the variably shunting the cascode node of the TIA decreases an impedance of the cascode node by a factor of 2 or less, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Vera Villarroel et al. (US 2020/0092010 A1, of record), hereinafter Vera Villarroel in view of Singhal et al. (US 20230231522 A1, of record, hereinafter, Singhal) and in view of Liu et al. (US 20240322772 A1, hereinafter Liu) and in view of Bae et al. (S 20090072904 A1 of record), hereinafter, Bae and further in view of Brekelmans et al. (US 20150381129 A1, hereinafter Brekelmans).
Regarding claim 18:
Vera Villarroel discloses in Fig. 6 (transimpedance amplifier 2 and variable gain amplifier 3 which have similar arrangement as shown Fig. 2 of the examining application, namely, Front-end TIA and VGA) an apparatus or method comprising:
a transimpedance amplifier “TIA” (2) and a variable gain amplifier (3) form a transimpedance amplifier circuit except for a cascode circuit including a cascode node; and a first tunable element connected to tunably shunt the cascode node to vary a voltage gain of the TIA circuit.
Singhal discloses in Fig. 7 adjustable gain amplifier comprising:
Transistors M1, M2 and a cascode circuit including a cascode node (annotated node CASN1, CASN2); and a first tunable element (controllable transistor Madj’) connected to tunably shunt the cascode node to vary a voltage gain of the gain amplifier.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced a generic variable gain amplifier as taught by Vera Villarroel with specific variable gain amplifier as taught by Singhal. Such a modification would have imparted the advantages benefits of improving a wide range of gain attenuation can be achieved with fine resolution without negatively impacting the noise figure and frequency response between the high and low gain modes (Paragraph [0018]).
The combination (Vera Villarroel and Singhal) does not teach a current steering circuit.
Liu discloses in Fig. 2 an amplifier circuit comprising differential cascode amplification circuit 2 and current-steering structures 3 formed by a group of transistors connected to a cascode node.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of The combination (Vera Villarroel and Singhal) to have the current-steering circuits, as taught by Liu. Such a modification would have imparted the advantageous benefit of improving gain and phase shift fluctuation of the amplification circuit during switching between different gain states is significantly reduced; moreover, the current-steering-based single-stage differential cascode structure in the present disclosure has advantages of simple circuit structure design, small module layout area and low power consumption (Paragraph [0069]), as taught by Liu to the combination (Vera Villarroel and Singhal), thereby suggesting the obviousness of such a modification.
The combination (Vera Villarroel and Singhal and Liu) discloses the limitations as applied in claim 1 except for a second tunable element connected to shunt a load resistor of the TIA circuit.
Bae discloses in Fig. 3 a variable gain amplifier comprising a transistor M2 being connected between output terminals of transistors Q1 and Q2 and load resistors 302 and 304 being connected being connected to transistors 314, 316 as shown in Fig. 3 of Base.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination circuit of Vera Villarroel in view of Singhal with the teaching transistors M2 and load resistors 302 and 304 as taught by Base. Such a modification would have imparted the advantages benefits of improving gain control linearity (paragraph [0023], a load resistance made up of resistors 302, 304, is provided. In addition, a load resistance is also coupled between the collectors of the pair of transistors 314, 316, the load resistance being a second FET M.sub.2 312 (P-type FET, or PMOS). As FET 312 is turned on, the gain G of the amplifier is decreased. The second gain control is optionally included to enhance the gain control linearity, as well as to extend the range of the gain factor G and to reduce peaking, as described herein).
Accordingly, as an obvious consequence above, the combination further discloses the method comprising variably shunting a load resistor circuit of the TIA to reduce the TIA gain by a first amount; and variably shunting cascode node of the TIA to reduce the TIA gain by a second amount; and (see current steering circuit) steering a tunable fraction of a current flowing through the cascode node away from the load resistor to reduce the TIA gain by a third amount additional to the first and second amounts.
The combination (Vera Villarroel, Singhal, Liu and Bae) the limitations as discussed above except for a feedback resistor.
Brekelmans discloses in Fig. 1, a transimpedance amplifier circuit comprising a variable feedback resistor 114.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination circuit of (Vera Villarroel, Singhal, Liu and Bae) to include a variable feedback resistor as taught by Brekelmans in order to provide the benefits of adjusting gain and achieve a variable impedance in the feedback (see paragraph [0025]).
Accordingly, as an obvious consequence above the combination further discloses a method for controlling a trans-impedance of a trans-impedance amplifier (TIA), the TIA comprising a cascode circuit (Fig. 7 of Singhal) having a cascode node and a feedback resistor (Fig. 1 of Brekelmans), the method comprising:tuning the feedback resistor to vary the trans-impedance of the TIA; and varying a voltage gain of the cascode circuit in three distinct stages as the feedback resistor is being tuned, the three distinct stages comprising: a first distinct stage of variably shunting a load resistor (Fig. 3 of Bae) of the cascode circuit to reduce the voltage gain by a first amount;a second distinct stage (Madj’ of Fig. 7 of Singhal) of variably shunting the cascode node to reduce the voltage gain by a second amount; and a third distinct stage (steering current circuit 3, Fig. 2 of Liu) of steering a tunable fraction of a current flowing through the cascode node away from the load resistor to reduce the TIA gain by a third amount additional to the first and second amounts.
Regarding claim 19:
The combination (Vera Villarroel, Singhal, Liu and Bae and Brekelmans) further discloses wherein each of the first, second, and third distinct stages change the voltage gain of the cascode circuit by at most 12 dB (Singhal, see paragraph [0040], gain adjustment transistors,10-20 dB).
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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