DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 8-9 & 11-16 have been considered but are moot because the new ground of rejection and newly found references US 20230231522 A1 and US 20090072904 A1, thus moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 9 & 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Vera Villarroel et al. (US 2020/0092010 A1, of record), hereinafter Vera Villarroel in view of Singhal et al. (US 20230231522 A1), hereinafter, Singhal.
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Fig. 6 of Vera Villarroel
Regarding claims 1 & 14:
Vera Villarroel discloses in Fig. 6 ( transimpedance amplifier 2 and variable gain amplifier 3 which having similarly arrangement as shown Fig. 2 of the examining application, namely, Front-end TIA and VGA) an apparatus or method comprising:
a transimpedance amplifier “TIA” (2) and a variable gain amplifier (3) form a transimpedance amplifier circuit except for a cascode circuit including a cascode node; and a first tunable element connected to tunably shunt the cascode node to vary a voltage gain of the TIA circuit; and a current steering circuit.
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Singhal discloses in Fig. 8 adjustable gain amplifier comprising:
a cascode circuit including a cascode node (annotated node CASN1, CASN2); and a first tunable element (controllable transistor Madj’) connected to tunably shunt the cascode node to vary a voltage gain of the TIA circuit (paragraph [0062] of Singhal states “input transistors M1 and M2 may be coupled to cascode transistors Mcas1 and Mcas2 and cross-coupled with capacitance neutralization transistors M3 and M4. P-type gain adjustment transistor Madj′ may be coupled across the source terminals of the cascode transistors. N-type gain adjustment transistors Madj1 and Madj2 may be coupled (shunted) in parallel with source resistors Rbig1 and Rbig2, respectively”; and
a current steering circuit (form by transistors Madj1, Madj2, resistors Rbig1 and Rbig2 and also see paragraph [0061], which states “Control voltage Vcon may be asserted (driven low) to activate transistor Madj′ in the low gain mode. Turning on transistor Madj′ steers or diverts some of the current that otherwise would have flowed from the input transistors to the output terminals but instead through transistor Madj′. Diverting a fraction of the current away from the output terminals effectively decreases the gain of amplifier 51 and decreases its output power).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced a generic variable gain amplifier as taught by Vera Villarroel with specific variable gain amplifier as taught by Singhal. Such a modification would have impart the advantages benefits of improving the overall gain of amplifier, noise characteristics, and stability and performance (see paragraph [0044], which states “which improves the overall gain of amplifier 51. Thus, transistors M3 and M4 are sometimes referred to as parasitic capacitance neutralization transistors or capacitance cancellation transistors” and paragraph [0051], improve noise characteristics).
Regarding claims 2 & 3:
The combination (Vera Villarroel in view of Singhal) discloses the apparatus of claim 1 wherein the first tunable element comprises a first transistor (controllable transistor Madj’, Fig. 8 of Singhal, see paragraph [0060], transistor Madj’, low impedance, since the transistor Madj’ which having an arrangement similarly to the applicant’s Fig. 4, transistor Vg1, thus the controllable or adjustable transistor Madj’s which is capable of operatable to very impedance of the CAS1, CAS2 node to 6dB or 12dB, see paragraph [0040], gain adjustment transistors, 2dB, 4dB, 10dB and 10-20dB) operable to vary an impedance of the cascode node by at most 6 dB; and (Claim 3) The apparatus of claim 1 wherein the first tunable element comprises a first transistor operable to vary an impedance of the cascode node by at most 12 dB (as above discussion, controllable or adjustable transistor Madj’ which is capable of tuning or vary impedance), it is noted that the applicant used same transistor M1 as shown in Fig. 4 of the applicant to vary multiple different impedance of the cascode node by 6dB or 12dB.
Regarding claim 4:
The combination (Vera Villarroel in view of Singhal) discloses the apparatus of claim 1 wherein the first tunable element is a MOS transistor (transistor Madj’, Fig. 8 of Vera Villarroel).
Regarding claim 9 & 16, the combination (Vera Villarroel in view of Singhal) discloses further comprising a coherent optical receiver (Fig. 6 of Vera Villarroel, paragraph [0029], which states “a photonic integrated circuit (PIC) 6 including one or more transducers, such as one or more photodetectors, and preferably a pair of photodiodes”) including a balanced photodetector pair connected to the TIA circuit.
Regarding claim 15, the combination (Vera Villarroel in view of Singhal) discloses wherein the VGA comprises:
a cascode circuit (includes transistor Madj’, for adjusting gain) including a cascode node (annotated node, CASN1 and CASN2); and the tunable internal AC shunt comprises a tunable element (transistor Madj’) connected to variably shunt the cascode node (annotated CASN1, CASN2).
Claims 5 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Vera Villarroel et al. (US 2020/0092010 A1, of record),hereinafter Vera Villarroel in view of Singhal et al. (US 20230231522 A1), hereinafter, Singhal and further in view of Bae et al. (S 20090072904 A1), hereinafter, Bae.
Regarding claim 5:
The combination (Vera Villarroel in view of Singhal) discloses the limitations as applied in claim 1 except for a second tunable element connected to shunt a load resistor of the TIA circuit.
Bae discloses in Fig. 3 a variable gain amplifier comprising a transistor M2 being connected between output terminals of transistors Q1 and Q2 and load resistors 302 and 304 being connected being connected to transistors 314, 316 as shown in Fig. 3 of Base.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination circuit of Vera Villarroel in view of Singhal with the teaching transistors M2 and load resistors 302 and 304 as taught by Base. Such a modification would have impart the advantages benefits of improving gain control linearity (paragraph [0023], a load resistance made up of resistors 302, 304, is provided. In addition, a load resistance is also coupled between the collectors of the pair of transistors 314, 316, the load resistance being a second FET M.sub.2 312 (P-type FET, or PMOS). As the FET 312 is turned on, the gain G of the amplifier is decreased. The second gain control is optionally included to enhance the gain control linearity, as well as to extend the range of the gain factor G and to reduce peaking, as described herein).
Regarding claim 8, the combination ((Vera Villarroel in view of Singhal and Bae) discloses the apparatus of claim 5, wherein each of the first (control or adjustable transistor Madj’, Singhal) and second tunable (controllable or adjustable or tunable transistor M2 of Base) elements are capable of configuring to reduce the voltage gain of the TIA circuit by no more than 12 dB (see paragraph [0040], gain adjustment transistors, 2dB, 4dB, 10dB and 10-20dB).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Vera Villarroel et al. (US 2020/0092010 A1, of record), hereinafter Vera Villarroel in view of Singhal et al. (US 20230231522 A1), hereinafter, Singhal and further in view of Bae et al. (US 20090072904 A1), hereinafter, Bae.
Regarding claim 11:
Vera Villarroel discloses in Fig. 6 ( transimpedance amplifier 2 and variable gain amplifier 3 which having similarly arrangement as shown Fig. 2 of the examining application, namely, Front-end TIA and VGA) an apparatus or method comprising:
a transimpedance amplifier “TIA” (2) and a variable gain amplifier (3) form a transimpedance amplifier circuit except for a cascode circuit including a cascode node; and a tunable element connected to tunably shunt the cascode node to vary a voltage gain of the TIA circuit; and a current steering circuit.
Singhal discloses in Fig. 8 adjustable gain amplifier comprising:
a cascode circuit including a cascode node (annotated node CASN1, CASN2); and a tunable element (controllable transistor Madj’) connected to tunably shunt the cascode node to vary a voltage gain of the TIA circuit (paragraph [0062] of Singhal states “input transistors M1 and M2 may be coupled to cascode transistors Mcas1 and Mcas2 and cross-coupled with capacitance neutralization transistors M3 and M4. P-type gain adjustment transistor Madj′ may be coupled across the source terminals of the cascode transistors. N-type gain adjustment transistors Madj1 and Madj2 may be coupled (shunted) in parallel with source resistors Rbig1 and Rbig2, respectively”; and
a current steering circuit (form by transistors Madj1, Madj2, resistors Rbig1 and Rbig2 and also see paragraph [0061], which states “Control voltage Vcon may be asserted (driven low) to activate transistor Madj′ in the low gain mode. Turning on transistor Madj′ steers or diverts some of the current that otherwise would have flowed from the input transistors to the output terminals but instead through transistor Madj′. Diverting a fraction of the current away from the output terminals effectively decreases the gain of amplifier 51 and decreases its output power).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced a generic variable gain amplifier as taught by Vera Villarroel with specific variable gain amplifier as taught by Singhal. Such a modification would have impart the advantages benefits of improving the overall gain of amplifier, noise characteristics, and stability and performance (see paragraph [0044], which states “which improves the overall gain of amplifier 51. Thus, transistors M3 and M4 are sometimes referred to as parasitic capacitance neutralization transistors or capacitance cancellation transistors” and paragraph [0051], improve noise characteristics).
The combination ((Vera Villarroel in view of Singhal and Bae) is silent on the limitations of further comprising at least one of:
variably shunting a load resistor of the TIA; and
steering a tunable fraction of a current flowing through the cascode node away from the load resistor.
Bae discloses in Fig. 3 a variable gain amplifier comprising a transistor M2 being connected between output terminals of transistors Q1 and Q2 and load resistors 302 and 304 being connected being connected to transistors 314, 316 as shown in Fig. 3 of Base.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination circuit of Vera Villarroel in view of Singhal with the teaching transistors M2 and load resistors 302 and 304 as taught by Base. Such a modification would have impart the advantages benefits of improving gain control linearity (paragraph [0023], a load resistance made up of resistors 302, 304, is provided. In addition, a load resistance is also coupled between the collectors of the pair of transistors 314, 316, the load resistance being a second FET M.sub.2 312 (P-type FET, or PMOS). As the FET 312 is turned on, the gain G of the amplifier is decreased. The second gain control is optionally included to enhance the gain control linearity, as well as to extend the range of the gain factor G and to reduce peaking, as described herein).
Accordingly, as an obvious consequence above, the combination further discloses the method for controlling a trans-impedance amplifier (TIA) gain, the method comprising:
variably shunting a cascode node of the TIA: and
further comprising at least one of:
variably shunting (transistor M2) a load resistor (load resistors 302, 304) of the TIA; and
steering (a current steering circuit which form by transistors Madj1, Madj2, resistors Rbig1 and Rbig2 and also see paragraph [0061], which states “Control voltage Vcon may be asserted (driven low) to activate transistor Madj′ in the low gain mode. Turning on transistor Madj′ steers or diverts some of the current that otherwise would have flowed from the input transistors to the output terminals but instead through transistor Madj′. Diverting a fraction of the current away from the output terminals effectively decreases the gain of amplifier 51 and decreases its output power) a tunable fraction of a current flowing through the cascode node away from the load resistor.
Regarding claim 12:
The combination (Vera Villarroel in view of Singhal further in view of Bae) discloses the method of claim 11 wherein the variably shunting (transistor M2 of Base, Fig.2) a load resistor (resistors 302 and 304) of the TIA decreases the TIA gain by a first amount, and wherein at least one of the variably shunting a cascode node (CASN1, CASN2, Fig. 8 of Singhal) of the TIA and the steering a tunable fraction of a current flowing through the cascode node away from the load resistor further decreases the TIA gain by a second amount additional to the first amount (it is note that no specific first and second amount of gain being defined by the applicant).
Regarding claim 13:
The combination (Vera Villarroel in view of Singhal further in view of Bae) discloses the method of claim 12, wherein the variably shunting a cascode node (CASN1, CASN2, annotated Fig. 8, Singhal) of the TIA decreases the TIA gain by the second amount additionally to the first amount, and the steering (a current steering circuit which form by transistors Madj1, Madj2, resistors Rbig1 and Rbig2 and also see paragraph [0061], which states “Control voltage Vcon may be asserted (driven low) to activate transistor Madj′ in the low gain mode. Turning on transistor Madj′ steers or diverts some of the current that otherwise would have flowed from the input transistors to the output terminals but instead through transistor Madj′. Diverting a fraction of the current away from the output terminals effectively decreases the gain of amplifier 51 and decreases its output power) a tunable fraction of a current flowing through the cascode node away from the load resistor further decreases the TIA gain by a third amount (it is noted that no specific third amount defined by the applicant) additional to the first and second amounts.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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