DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/21/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the comparison voltage generation circuit further comprises: a seventh transistor having a base or a gate connected to a base or a gate of the third transistor, and a collector or a drain connected to the emitter or the source of the second transistor, and a second resistance element between the collector or the drain of the seventh transistor, and the base or gate of the seventh transistor” in Claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 & 7-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamashita (US 6,731,171 B2).
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Regarding claim 1, Yamashita (Figs. 2, 4, 6, 8 & 9) discloses a power amplifier circuit, comprising:
a first transistor (10 of Fig. 2) having a base (base of transistor 10) or a gate to which a bias current or a bias voltage is supplied, and being configured to amplify an input signal and to output a first current (output signal from collector of transistor 10);
a second transistor (transistor 52 of Fig. 2) having an emitter (emitter of transistor 52) or a source connected to the base (base of transistor 10) or the gate of the first transistor (10), and being configured to supply the bias current or the bias voltage from the emitter (emitter of transistor 52) or the source to the base or the gate of the first transistor (base of transistor 10);
a comparison voltage generation circuit (e.g. circuit 5 include transistor 50 & 51) comprising a third transistor (transistor 50) connected to a base or a gate of the second transistor, and being configured to generate a comparison voltage based on a second current (Ib) flowing through the third transistor; and
a comparison circuit (a circuit includes detection circuit 17, & error amplifier circuit 4) connected to the base or the gate of the second transistor (52), being supplied with the comparison voltage and a reference voltage (reference potential signal which provides to the gate terminal of the transistor 47 by capacitor 48, it is noted that error amplifier form by transistor 46 and 46 and wherein the error amplifier comparing signals that receiving at its gate terminals), and being configured to decrease a third current (current goes to the base of transistor 52) supplied to the base or the gate of the second transistor (transistor 52) as the second current increases, based on the comparison voltage and the reference voltage.
Regarding claim 2, Yamashita (Figs. 2, 4, 6, 8 & 9) discloses the power amplifier circuit according to Claim 1, further comprising:
a bias source (see Figs. 8 & 9, where circuit 118 provide control signal to control terminal “CONTROL SIGNAL IN as shown in Fig. 8) connected to the base or the gate of the second transistor (transistor 10 of Fig. 2) and being configured to generate the third current, wherein the comparison circuit (a circuit includes detection circuit 17, & error amplifier circuit 4) is configured to generate a fourth current (Icp) based on a differential voltage that is a difference between the comparison voltage and the reference voltage, and is configured to decrease the third current by removing the fourth current from the third current.
Regarding claim 3, Yamashita discloses the power amplifier circuit according to Claim 1, wherein the comparison voltage generation circuit (circuit 5 of Fig. 2) is configured to decrease the comparison voltage along with a temperature increase of the first transistor (Col. 5, line25-30, voltage of the transistors 50 and 51 lowers and temperature rises).
Regarding claim 7, Yamashita discloses the power amplifier circuit according to Claim 1, further comprising:
a bias control circuit source (see Figs. 8 & 9, where circuit 118 provide control signal to control terminal “CONTROL SIGNAL IN as shown in Fig. 8) configured to supply a bias control signal to the second transistor (transistor 52 of Fig. 2).
Regarding claim 8, Yamashita discloses the power amplifier circuit according to Claim 2, wherein the comparison circuit comprises:
a sixth transistor (transistor 47 of Fig. 2) having a base or a gate to which the reference voltage is supplied, and a seventh transistor (transistor 46 of Fig. 2) having a collector or a drain through which the fourth current (Icp) flows.
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 9-16 are allowed.
Upon conclusion of a comprehensive search of the pertinent prior art, the Office indicates that the claims are allowable.
The prior art when taken alone, or, in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant. Added primarily for emphasis, the claim recitations “a fourth transistor having a base or a gate to which a second bias current or a second bias voltage is supplied, and a collector or a drain connected to the base or the gate of the first transistor, and being configured to amplify an input signal and to output the first signal; a fifth transistor having an emitter or a source connected to the base or the gate of the fourth transistor, and being configured to supply the second bias current or the second bias voltage from the emitter or the source to the base or the gate of the fourth transistor” in claim 9 is not found in the prior art of record.
Claims 10-16 are allowable as being dependent of claim 9.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ANDREA J LINDGREN BALTZELL can be reached at (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843