DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant previously elected Group I.
Response to Arguments
Applicant's arguments filed 8/12/2026, have been fully considered but they are not persuasive.
Applicant’s first argument regarding claim 1 is that Li fails to disclose an LDO circuit configured to adjust the supply voltage responsive to a DC voltage at an output of the TIA because Li’s feedback mechanism relies on data slicers, a logic device, and a DAC, rather than directly sensing an analog DC voltage at the output of the TIA
This argument is not persuasive. Claim 1 does not require the LDO circuit to directly or solely sense the DC voltage at the output of the TIA, nor does the claim preclude intervening elements between the TIA output and the LDO circuit. Rather, claim 1 recites that the LDO circuit is configured to adjust the supply voltage “responsive to a DC voltage at an output of the TIA.”
As discussed in the rejection, Li, Fig. 7, discloses that LDO 140 is controlled via DAC 175 and logic device 140 based on information derived from the output of TIA 120 through data slicers 130, 150. Thus, the adjustment of the supply voltage by LDO 140 is responsive to information derived from the DC voltage at the output of TIA 120, notwithstanding the presence of intervening data slicers, logic device, and DAC. Applicant’s argument that the present invention directly senses an analog DC voltage therefore relies on a limitation that is not recited in claim 1. Accordingly, applicant’s argument is not persuasive.
Applicant’s second argument regarding claim 2 is that Li allegedly does not adjust its supply voltage responsive to a DC voltage as required by claim 1, and Li also fails to disclose adjusting the supply voltage to lessen variations of the DC voltage at the output of the TIA.
This argument is not persuasive. As discussed above with respect to claim 1, Li’s LDO adjustment is responsive to information derived from the DC voltage at the output of TIA 120 and claim 1 does not require direct analog sensing of the DC voltage. Further, as set forth in the rejection of claim 2, Li discloses detecting errors/variations in the signal derived from the output of TIA 120 through data slicers 130, 150 and logic device 140 and adjusting the supply voltage via DAC 175 and LDO 140 in response to the detected errors, thereby lessening variations in the DC voltage component at the output of the TIA. Accordingly, Applicant’s argument with respect to claim 2 is not persuasive.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by
Li et al. (US 20170359119 A1)
Regarding claim 1, Li, fig. 7, discloses a trans-impedance amplifier (TIA) (120) ; and, a low drop-out (LDO) circuit (140) for providing a supply voltage to the TIA (120), the LDO circuit being configured to adjust the supply voltage, wherein LDO 140 is controlled via DAC 175 and logic device 140 which is responsive to a DC voltage at an output of the TIA. Li, fig. 7, further discloses that LDO 140 provides for adjusting the supply voltage based on a control signal derived from the output of TIA 120 via data slicer 130, 150, logic device 140, and DAC 175.
Regarding claim 2, Li, Fig. 7 discloses detecting variations (errors) in a signal derived from the TIA output via data slicer (130) and logic device (140), and the supply voltage is adjusted via DAC (175) and LDO (140) in response to the detected errors, thereby lessening variations in the DC voltage component at the output of the TIA. (see abstract, [0037], line 4 – 6), as required by the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 4, 5 are rejected under 35 U.S.C. 103 as being unpatentable over
Li et al. (US 20170359119 A1) in view of Vangara (US 20220140791 A1)
Regarding claim 3, Li Fig. 7 discloses an LDO control path associated with a TIA (120), as discussed above with respect to claim 1. However, Li doesn’t disclose wherein the LDO circuit is configured to control a DC common-mode output voltage of the TIA.
Vangara (see Abstract; Fig. 6) discloses, an LDO regulator circuit (see the abstract), configured to maintain load regulation and reduce output voltage variation, wherein the circuit includes a feedback control loop having an amplifier (204), a pass device (M1), and a resistor network (206) configured to set an output voltage relative to a reference voltage (Vref1). Such feedback-based control of the output voltage relative to a reference inherently controls a DC component of the output voltage, corresponding to a common-mode voltage.
It would have been obvious to a person of ordinary skill in the art to utilize Vangara’s feedback control loop in Li’s LDO control path to control a DC voltage at the output of the TIA (120) in Li, including providing for a common-mode component, to improve regulation accuracy and reduce output variation, as taught by Vangara.
Regarding claim 4, Li, Fig. 7, discloses an LDO control circuit (140) provides a regulated supply voltage to the TIA (120), as discussed above. However, Li doesn’t disclose the LDO circuit comprises an operational amplifier configured to adjust the DC voltage at the output of the TIA towards a reference voltage.
Vangara, (see abstract, fig. 6), as discussed above, discloses and LDO circuit including an amplifier (204), resistor network (206) at node (X), pass device (M1), and reference voltages (Vref1, Vref2), wherein the amplifier (204) is configured to compare a feedback signal with the reference voltage and adjust a DC voltage.
It would have been obvious to a person of ordinary skill in the art to incorporate Vangara’s amplifier (204) into Li’s LDO control circuit (140) to adjust the DC voltage supplied to the TIA (Li, Fig. 7, 120), to improve regulation accuracy and stability as taught by Vangara.
Regarding claim 5, Li, Fig. 7, discloses an LDO control circuit (140) associated with the TIA (120), as discussed above. However, Li doesn’t disclose an input DC current cancellation circuit configured to adjust a DC input voltage of the TIA towards the reference voltage.
Vangara, (Fig. 6), discloses an offset current generator (602) that receives a sensed current derived from the load current (paragraph [0047], line 11-15) and generates a corresponding offset current (paragraph [0048], lines 1 – 3), that is applied to modify the input current conditions of the TIA and create a voltage offset relative to a reference voltage (paragraph [0049], lines 2 – 4). This operation adjusts a DC input condition of the circuit through current-based compensation toward the reference, corresponding to an input DC current cancellation function.
It would have been obvious to a person of ordinary skill in the art to incorporate Vangara’s offset current generator (602) into Li’s fig. 7, LDO circuit (140), associated with the TIA (120), to provide an input DC current cancellation function at the input of the TIA to compensate for current variations and improve regulation accuracy, as taught by Vangara.
Claims 6, 12 are rejected under 35 U.S.C. 103 as being unpatentable over
Li et al. (US 20170359119 A1) in view of Xu et al. (Pat No. US 11621683 B2)
Regarding claim 6, Li, Fig. 7), discloses a TIA (120) providing output signals via data slicers (130, 150), corresponding to differential outputs at the (+,-) terminals. However, Li doesn’t disclose the DC voltage at an output of the TIA is common-mode DC voltage at the output of the TIA.
Xu, Fig. 3, discloses a common-mode feedback (CMFB) circuit (44) configured to derive a common-mode signal from differential output nodes and control the output voltage based on the common-mode signal (Xu, column 4, lines 51 – 58, 66, 67; column 5, lines 1 – 10)
It would have been obvious to a person of ordinary skill in the art to incorporate Xu’s CMFB circuit (44) into Li’s TIA output to regulate the output DC voltage as a common-mode DC voltage, thereby improving stability and reducing offset effects in the output signal, as taught by Xu.
Regarding claim 12, Li, Fig. 7 discloses an LDO control circuit (140) configured to provide a supply voltage to the TIA (120) via a control path including data slicer (130, 150), logic device (140), and DAC (175). However, Li doesn’t disclose the LDO circuit is configured to provide a common- mode feedback from the output of the TIA to regulate the supply voltage.
Xu Fig.3 discloses a common-mode feedback block (CMFB 44) configured to derive a common-mode signal from differential output nodes OUTP (42A) and OUTN (42B).
It would have been obvious to a person of ordinary skill in the art to incorporate Xu’s common-mode feedback (CMFB 44), which derives a common-mode signal from differential outputs and applies common-mode feedback based on the output to control voltage conditions (Xu, column 4, lines 51 – 55; CMFB 44), into Li’s LDO control path (Li, fig. 7, 130, 140, 175) to regulate the supply voltage based on a common-mode signal from the TIA output, thereby improving regulation stability and accuracy, as taught by Xu.
Claims 8 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over
Li et al. (US 20170359119 A1) in view of Mayerl et al. (US 20220147087 A1)
Regarding claim 8, Li (fig. 7), discloses a trans-impedance amplifier (TIA) (120) and an LDO circuit (140) configured to provide a supply voltage to the TIA, wherein the supply voltage is adjusted responsive to detected operating conditions of the TIA system through feedback from logic device (140) and DAC (175). However, Li does not disclose that the LDO circuit is configured to regulate less than 50% of a supply DC current of the TIA, as recited in claim 8.
Mayerl discloses configuring regulation circuitry such that current regulation occurs over predefined operating percentages, including between 20% and 50% of operation (Mayerl, paragraph [0060]). Mayerl further discloses current sink circuitry (fig. 3, 108, 110) for regulating output behavior through controlled current regulation (paragraphs [0058 – 0060]).
It would have been obvious to one of ordinary skill in the art to configure the regulation behavior of Li using the proportional current regulation techniques of Mayerl in order to provide predictable and controllable current regulation behavior within predefined operating ranges.
Regarding claim 9, Li (fig. 7), discloses an LDO circuit (140) configured to regulate a supply voltage provided to TAI (120) through feedback control circuitry including DAC (175) and logic device (140). However, Li does not disclose that the LDO circuit is configured to regulate a first portion of a supply DC current of the TIA, and that the apparatus further comprises a current mirror for adding a second portion of the supply DC current to the first portion at a supply voltage node of the TIA, as recited in claim 9.
Mayerl discloses current sink circuitry and current mirror implementations for regulating output current behavior (paragraphs [0064 – 0067]. Mayerl further discloses that current sink may be formed as a current mirror and describes proportional current paths and current ratios between mirror branches (paragraph [0067]).
It would have been obvious to one of ordinary skill in the art to incorporate the current mirror regulation techniques of Mayerl into the regulated TIA supply arrangement of Li in order to achieve predictable proportional current regulation and improved control of supply current distribution.
Regarding claim 10, Li in view of Mayerl discloses the apparatus of claim 9. Mayerl, paragraph [0060], discloses configuring current regulation circuitry such that regulated current corresponds to less than 50% of operating current or operating duration. Because Mayerl regulates operation of the current sink circuitry over defined proportional operating ranges, one of ordinary skill in the art would understand the regulated current contribution likewise corresponds proportionally to the regulated operating percentage.
It would have been obvious to one of ordinary skill in the art to configure the first portion of the regulated supply DC current to be less than 50% of the supply DC current as recited in claim 10 in order to achieve controlled proportional current regulation.
Regarding claim 11, Li in view of Mayerl discloses the apparatus of claim 9 including a current mirror configured to provide supply current to a node. Mayerl further discloses current mirror circuitry including proportional current branches and current mirror ratios, paragraph [0067].
Therefore, it would have been obvious to provide a source of reference current coupled to an input of the current mirror in order to enable predictable mirrored current generation, as recited in claim 11.
Allowable Subject Matter
Claims 7 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to /NATASHA Y MARANO/ whose telephone number is (571)272-9512. The examiner can normally be reached Mon - Fri 7:30am - 3:30pm.
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/NATASHA Y MARANO/
Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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