DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 08/22/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/21/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 5-6, 8-10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (PG Pub 2015/0155203; hereinafter Chen) in view of Shih et al. (PG Pub 2018/0102311; hereinafter Shih).
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Regarding claim 1, refer to the Examiner’s mark-up of Fig. 10 provided above, Chen teaches a semiconductor package 66, comprising:
a first redistribution wiring layer (annotated “RDL-1” in Fig. 10 above) including first (top) and second surfaces (bottom) opposite to each other (see Fig. 10), wherein the first redistribution wiring layer includes a first chip mounting region (region below 24) and a second chip mounting region (region below 25) adjacent to the first chip mounting region (see Fig. 10), and wherein the first redistribution wiring layer includes a plurality of redistribution pads (42 in the top layer of RDL-1) that are exposed from the first surface (see Fig. 10);
a connection layer (annotated “connection” in Fig. 10 above) on the first surface of the first redistribution wiring layer (see Fig. 10), wherein the connection layer includes first connection pad structures (42 on bottom of connection) and second connection pad structures (42 on top of connection) wherein the first connection pad structures contact at least one of the plurality of redistribution pads on the first chip mounting region (see Fig. 10), and wherein the second connection pad structures contact at least one of the plurality of the redistribution pads on the second chip mounting region (see Fig. 10);
a first semiconductor chip 24 on the first chip mounting region on the connection layer (see Fig. 10), wherein the first semiconductor chip includes first chip pads 26 that are electrically connected to the first connection pad structures (see Fig. 10);
a second semiconductor chip 25 spaced apart from the first semiconductor chip on the second chip mounting region on the connection layer (see Fig. 10);
a molding member 40 on the first and second semiconductor chips on the connection layer (see Fig. 10); and
a second redistribution wiring layer (annotated “RDL-2” in Fig. 10 above) on the molding member (see Fig. 10).
Although, Chen teaches the second semiconductor chip 25 spaced apart from the first semiconductor chip 24, he does not explicitly teach the second semiconductor chip includes through electrodes that are electrically connected to the second connection pad structures; wherein the second redistribution wiring layer is electrically connected to the first redistribution wiring layer through the through electrodes.
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In the same field of endeavor, refer to Fig. 14-provided above, Shih teaches a semiconductor package comprising: a semiconductor chip 101 includes through electrodes 110 that are electrically connected to second connection pad structures 714; wherein a second redistribution wiring layer 900 is electrically connected to a first redistribution wiring layer 700 through the through electrodes (see Fig. 14).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second semiconductor chip of Chen comprise the through electrodes, as taught by Shih, to provide electrical communications between the first and second RDL.
Regarding claim 2, refer to the figures cited above, Chen and Shih teach each of the second connection pad structures (42 on top of connection-Chen) includes an upper pad pattern (712-top layer of Shih) that contacts at least one of the through electrodes 110 and a lower pad pattern (714 via portion) that is on the upper pad pattern and contacts at least one of the plurality of redistribution pads 718-Shih (see Fig. 12).
Regarding claim 3, refer to the figures cited above, Chen and Shih teach the upper pad pattern (712-top layer of Shih) has a first width in a horizontal direction parallel to the first surface (see Fig. 12), and the lower pad pattern (via portion of 714) has a second width in the horizontal direction greater than the first width (see Fig. 12). Although, Shih teaches the second width in the horizontal direction less than the first width. He does not explicitly teach the second width in the horizontal direction greater than the first width.
However, one of ordinary skill in the art would have found it obvious to alter the size/proportion of the second width to be greater than, less than or equal to the first width, since the court has held changes in size/proportion normally require only ordinary skill in the art and hence are considered routine expedients are discussed below (MPEP § 2144). Furthermore, according to MPEP § 2144.05(IV)(A) “[W]here the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation), Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 5, refer to the figures cited above, in the combination of Chen and Shih, Shih teaches a distance between a first 11 and a second semiconductor chips 12 in a horizontal direction parallel to the first surface (top) is within a range of 50micrometers (um) to 200µm (para [0052]). Shih teaches “the solder balls 810 may have a ball pitch P.sub.2 that is equal to the ball pad pitch (smaller than 100 micrometers) on a printed circuit board (PCB) or a system board”. One of ordinary skill in the art could extrapolate that the distance between the chips would also fall within this range (see Fig. 13). Furthermore, one of ordinary skill in the art would minimize the space between dies to reduce the overall package size.
Regarding claim 6, refer to the figures cited above, in the combination of Chen and Shih, Chen teaches an upper surface of the first semiconductor chip has a surface area of a first size SI, wherein an upper surface of the second semiconductor chip has a surface area of a second size S2, and wherein a ratio of the second size S2 to the first size S1 is the same.
Although, Chen teaches an upper surface of the first semiconductor chip has a surface area of a first size SI, wherein an upper surface of the second semiconductor chip has a surface area of a second size S2, and wherein a ratio of the second size S2 to the first size S1 are the same, he does not teach the ratio of the second size S2 to the first size S1 is within a range of 0.01 to 0.9.
However, one of ordinary skill in the art would have found it obvious to alter the size/proportion of the ratio of the second size S2 to the first size S1 to be within a range of 0.01 to 0.9 since, the court has held changes in size/proportion normally require only ordinary skill in the art and hence are considered routine expedients are discussed below (MPEP § 2144).
Furthermore, according to MPEP § 2144.05(IV)(A) “[W]here the facts in a prior legal decision are sufficiently similar to those in an application under examination, the examiner may use the rationale used by the court. Examples directed to various common practices which the court has held normally require only ordinary skill in the art and hence are considered routine expedients are discussed below.” See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation), Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree “will not sustain a patent”); and In re Williams, 36 F.2d 436, 438 (CCPA 1929) (“It is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions.”).
Regarding claim 8, refer to the figures cited above, in the combination of Chen and Shih, Chen teaches a first bonding pad 41 in the first redistribution wiring layer (in “RDL”); and an external connection bump 46 on the first bonding pad (indirectly), wherein the first bonding pad is exposed from the second surface (bottom) of the first redistribution wiring layer (see Fig. 10).
Regarding claim 9, refer to the figures cited above, in the combination of Chen and Shih, Chen teaches a third semiconductor chip 58 on the second redistribution wiring layer (“RDL-2”) (see Fig. 10).
Regarding claim 10, refer to the figures cited above, in the combination of Chen and Shih, Shih teaches a protective layer 200 on an upper surface of a second semiconductor chip 101; a first pad pattern 208 penetrating the protective layer (see Fig. 14); and a second pad pattern 210 on the first pad patterns, wherein the second pad pattern contacts the second redistribution wiring layer 900 (see Fig. 14). It would have been obvious to one of ordinary skill in the art to incorporate the protective layer of Shih, above the second semiconductor die of Chen, to provide additional mechanical support to the second semiconductor chip.
Regarding claim 20, refer to the Examiner’s mark-up of Fig. 10 provided above, Chen teaches a semiconductor package 66, comprising:
a lower redistribution wiring layer (annotated “RDL-1”) that includes first (top) and second surfaces (bottom) opposite to each other (see Fig. 10), wherein the lower redistribution wiring layer includes a first chip mounting region (region below 24) and a second chip mounting region (region below 25) that is adjacent to the first chip mounting region (see Fig. 10), wherein the lower redistribution wiring layer includes a plurality of first redistribution pads 42 (not connecting with 46) that are exposed from the first surface (see Fig. 10), a plurality of second redistribution pads that are exposed from the second surface 42 (exposed to 46), and conductive connection members 46 respectively provided on the plurality of second redistribution pads (see Fig. 10);
a connection layer (annotated “connection” in Fig. 10 above) on the first surface of the lower redistribution wiring layer (see fig. 10), wherein the connection layer includes first connection pad structures (42-horizontal portion) and second connection pad structures (42-vertical portion), wherein the first connection pad structures contact at least one of the plurality of first redistribution pads on the first chip mounting region (see Fig. 10), wherein the second connection pad structures contact at least one of the plurality of second redistribution pads on the second chip mounting region (see Fig. 10); a first semiconductor chip 24 on the first chip mounting region of the connection layer and electrically connected to the first connection pad structures (see Fig. 10); a second semiconductor chip 25 on the second chip mounting region of the connection layer to be spaced apart from the first semiconductor chip (see Fig. 10); a molding member 40 on the first and second semiconductor chips on the connection layer (see Fig. 10); and an upper redistribution wiring layer (annotated “RDL-2” in Fig. 10 above) on the molding member and electrically connected to the lower redistribution wiring layer through the through electrodes.
Although, Chen teaches the second semiconductor chip 25 spaced apart from the first semiconductor chip 24, he does not explicitly teach the second semiconductor chip includes a plurality of through electrodes that are electrically connected to the second connection pad structures; wherein the second redistribution wiring layer is electrically connected to the first redistribution wiring layer through the through electrodes.
In the same field of endeavor, refer to Fig. 14-provided above, Shih teaches a semiconductor package comprising: a semiconductor chip 101 includes through electrodes 110 that are electrically connected to second connection pad structures 714; wherein a second redistribution wiring layer 900 is electrically connected to a first redistribution wiring layer 700 through the through electrodes (see Fig. 14).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the second semiconductor chip of Chen comprise the through electrodes, as taught by Shih, to provide electrical communications between the first and second RDL.
Allowable Subject Matter
3. Claims 4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 4, the first width of the upper pad pattern is within a range of 0.1 micrometers (um) to 50µm, wherein the second width of the lower pad pattern is within a range of 1.1 µm to 50µm, and wherein at least one of the through electrodes has a third width in the horizontal direction, and the third width is within a range of 10µm to 50µm.
Claim 7 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 7, a distance from the second surface of the first redistribution wiring layer to an upper surface of the second redistribution wiring layer in a vertical direction perpendicular to the first surface of the first redistribution wiring layer is within a range of 50micrometers (µm) to 200µm.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817