DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/02/2026 have been fully considered but they are only partially persuasive.
Applicant’s amendments to claims 5, 9, 12-13, and 15 overcome the previous 35 U.S.C. §112(d) rejections.
Applicant’s amendments to claim 9 do not conform with 37 C.F.R. §1.121 for proper formatting of adding and removing limitations and introduce the indefiniteness rejection as detailed below.
Applicant argues on page 9 that the previous office action fails to cite to a reference that discloses “using a mask on the top surface of the semiconductor body” as required by claim 1. Applicant’s statement is incorrect as the previous office action mailed 10/01/2025 page 5 last line recites in part “using a mask (gate 3) on the top surface” in the section determining of the scope and contents of the Frisina reference. Therefore, Applicant’s arguments that the burden to rebut the rejection have not been made and the next office action cannot be made final are not persuasive and the present office action is final. Although not currently claimed, one potential difference between Applicant’s disclosure and the teachings of Frisina is that Frisina uses the gate as an implant mask which differs from Applicant’s disclosure which teaches (e.g. FIG. 2a) a mask (25) which is removed (Fig. 2c) before forming a gate stack (Fig.3 gate 33) and therefore language of for example removing the mask and forming a gate electrode after implanting in the method claims may overcome the pending rejection, although further search and consideration is required to determine patentability.
Applicant argues on page 10 that the lobed body well 4a, 4b does not actually make the body well 4a, 4b into a “W-shaped second conductivity type region” as required by claim 1. The Examiner disagrees as the term “W-shaped second conductivity type region” cannot be interpreted so narrowly as requiring exactly a W-shape as then Applicant’s own disclosure fails to show a W-shape since the bottom of the two legs of the W are cut off in Applicant’s drawings:
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That is, Applicant’s implanted regions form a \_/\_/ shape whereas Frisina’s implanted regions form a ω shape. The Examiner interprets both Applicant’s and Frisina’s implanted shapes to generally fall within the scope of “W-shaped” under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111) and although not currently claimed, an amendment specifying the structural differences between Applicant’s disclosure and Frisina (e.g. “having flat sidewalls”) may overcome the pending rejection, although further search and consideration are required to determine patentability.
Lastly, Applicant argues on page 11-13 that if Frisina’s source 6a,6b regions are removed to allow a Schottky barrier to be formed between the gates 3 as described in Sdrulla, then there would be no W-shaped second conductivity region. The Examine agrees in that the applying the teachings of Sdrulla would involve dividing the W-shaped second conductivity region, which is the language required by Applicant’s claim 1 lines 15-17. Applicant’s claims do not require that the W-shaped is maintained after the etching/grinding step.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 9 recites in part “(Currently amended) A The vertical oriented semiconductor device of claim 5 obtained by the method in accordance with claim2further comprising:” which is indefinite since the amendments fail to conform to the requirements of 37 C.F.R. §1.121 for proper formatting of adding and removing limitations and it is unclear whether the claim depends on product-by-process of claim 5 or method of claim 2. Since claim 2 is directed to a method and claim 5 is directed to the device formed by a method, claim 9 is interpreted as depending on claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2008/0169517 A1 to Frisina et al., “Frisina”, in view of U.S. Patent Application Publication Number 2013/0313570 A1 to Sdrulla et al., “Sdrulla”.
Regarding claims 1 and 5, Frisina disclose a method (claim 1) of manufacturing a semiconductor device, being a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (¶ [0002],[0003]), and device obtained by the method (claim 5) comprising:
providing (FIG. 3) a semiconductor body (1) having a top surface and a current-accommodating region of a first conductivity type (e.g. 4H-SiC n-type substrate 1, ¶ [0043]);
implanting (FIG. 3 and FIG. 4) free charge carriers of a second conductivity type (aluminum/aluminium, ¶ [0047],[0048]), the second conductivity type opposite to the first conductivity type, using a mask (gate 3) on the top surface of the semiconductor body so that well regions (4a,4b), of the second conductivity type, are provided, wherein the well regions are laterally spaced so that the current-accommodating region is provided therein between at a particular depth in the semiconductor material (e.g. FIG. 4 region of n-type substrate 1 between 4a and 4b);
wherein the implanting is performed under at least two acute angles (FIG. 3 and FIG. 4 show two acute angles, ¶ [0047]) relative to a surface normal of the top surface so that a W-shaped second conductivity type region (4a,4b) is provided in the semiconductor material (see Examiner-annotated figure below):
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Frisina fails to clearly teach wherein the wells (4a,4b) are laterally spaced apart, and fails to teach a step of etching and/or grinding the semiconductor material from the top surface to the particular depth so that the W-shaped second conductivity region is divided into the well regions having the current-accommodating region therebetween.
Sdrulla teaches a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device (e.g. SiC VDMOS in FIG. 2) formed by (FIG. 4B) implanting such that the two wells (16, ¶ [0043]) are laterally spaced apart, and later (e.g. FIG. 6A) etching (notch 61, ¶ [0047]) the semiconductor material from a top surface to a particular depth so that the well regions (16) are divided into well regions having a current-accommodating region (16) therebetween (in order to integrate a Schottky barrier metal 36 in FIG. 6C, ¶ [0049]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Frisina by etching a notch between the semiconductor wells as taught by Sdrulla in order to integrate a trenched Schottky Barrier diode without any increase in device area (Sdrulla Abstract, ¶ [0002]-[0011]) and enable integration of an SBD with an SiC Vertical MOSFET without adding significant additional steps and further provide flexibility to optimize the diode current-carrying capability to adjust for application requirements. Such a merged configuration realizes both cost and space savings and provides performance improvement over two discrete devices (Sdrulla ¶ [0012]).
Regarding claims 2 and 9 insofar as definite, Frisina in view of Sdrulla yields the method in accordance with claim 1 and the device of claim 5, and Frisina further teaches wherein the method further comprises the step of (FIG. 7, FIG. 8): implanting further free charge carriers of the second conductivity type, using the mask (3) on the top surface of the semiconductor body, wherein the implanting is performed under at least two further acute angles (FIG. 7 and FIG. 8), relative to a surface normal of the top surface so that a further W-shaped first conductivity type region is provided in the semiconductor material.
Frisina fails to expressly state wherein the two further acute angles are different from the at least two acute angles.
However, Frisina teaches ranges for the two acute angles (¶ [0047],[0048]) and further two acute angles (¶ [0051],[0052]) which would include instances where the angle are different.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Frisina in view of Sdrulla with the sets of acute angles being different in order to control the resulting implant profile and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the angles determine the implant profiles making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claims 3 and 12, Frisina in view of Sdrulla yields the method in accordance with claim 1 and the device of claim 5, and Frisina further teaches (¶ [0001]) wherein the vertical oriented semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and Sdrulla further teaches wherein the vertical oriented semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (Sdrulla ¶ [0002]).
Regarding claims 4 and 13, Frisina in view of Sdrulla yields the method in accordance with claim 1 and the device of claim 5, and Frisina further teaches wherein the first conductivity type and the second conductivity type comprises any of N-type and P-type semiconductor material (implanting p-type aluminum/aluminium into n-type SiC substrate ¶ [0043]).
Regarding claim 6, Frisina in view of Sdrulla yields the method in accordance with claim 2, and Frisina further teaches wherein the implanted further free charge carriers in the semiconductor material (FIG. 7 and FIG. 8 regions 6a and 6b) have a depth that is less deep (as pictured) than compared to a depth of the implanted free charge carriers in the semiconductor material (wells 4a,4b).
Regarding claim 7, Frisina in view of Sdrulla yields the method in accordance with claim 2, and Frisina further teaches (¶ [0001]) wherein the vertical oriented semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and Sdrulla further teaches wherein the vertical oriented semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (Sdrulla ¶ [0002]).
Regarding claim 8, Frisina in view of Sdrulla yields the method in accordance with claim 2, and Frisina further teaches wherein the first conductivity type and the second conductivity type comprises any of N-type and P-type semiconductor material (implanting p-type aluminum/aluminium into n-type SiC substrate ¶ [0043]).
Regarding claims 10 and 15, Frisina in view of Sdrulla yields the method in accordance with claim 3 and the device of claim 12, and Frisina further teaches wherein the semiconductor device is a Silicon Carbide (SiC) MOSFET (Frisina ¶ [0002]), and Sdrulla further teaches wherein the semiconductor device is a Silicon Carbide (SiC) MOSFET (Sdrulla ¶ [0002]).
Regarding claim 11, Frisina in view of Sdrulla yields the method in accordance with claim 3, and Frisina further discloses wherein the method further comprises at least one step selected from the group consisting of:
(e.g. FIG. 2) growing or depositing gate oxides (2, ¶ [0043]),
(e.g. FIG. 2) manufacturing a gate conduction line (3, ¶ [0044]),
(e.g. FIG. 10) manufacturing interlayer dielectrics (7, ¶ [0060]), and
(e.g. FIG. 11) metal deposition (9, ¶ [0060]).
Regarding claim 14, Frisina in view of Sdrulla yields the method in accordance with claim 6, and Frisina further teaches (¶ [0001]) wherein the vertical oriented semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and Sdrulla further teaches wherein the vertical oriented semiconductor device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (Sdrulla ¶ [0002]).
Regarding claim 16, Frisina in view of Sdrulla yields the method in accordance with claim 10, and Frisina further teaches wherein the first conductivity type and the second conductivity type comprises any of N-type and P-type semiconductor material (implanting p-type aluminum/aluminium into n-type SiC substrate ¶ [0043]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891