Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, without traverse, of Group I-A, claims 1-11 in the reply filed on November 07th, 2025 is acknowledged. Non-elected invention, claims 12-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I-A, claims 1-11 as follows.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on July 21st, 2023, April 19th, 2024, May 17th, 2024 and September 05th, 2025 have been considered by the examiner.
Drawings
The drawings filed on 07/21/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Toyama (US 2017/0179026, hereinafter as Toya ‘026) in view of Kang (US 2017/0358590, hereinafter as Kang ‘590).
Regarding Claim 1, Toya ‘026 teaches a memory device, comprising:
a first-tier alternating stack of first insulating layers (Fig. 17C, (132); [0222]) and first electrically conductive layers (Fig. 17C, (146); [0228]) located over a substrate (9; [0163]);
a second-tier alternating stack of second insulating layers (Fig. 17C, (232); [0222]) and second electrically conductive layers (Fig. 17C, (246); [0228]) overlying the first-tier alternating stack;
memory openings (49; [0201]) vertically extending through the first-tier alternating stack and the second-tier alternating stack;
memory opening fill structures (55; [0203]) located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel (60; [0203]) and a vertical stack of memory elements (50; [0203]); and
a first support and contact assembly (488; [0244]) vertically extending through the first-tier alternating stack and the second-tier alternating stack.
Thus, Toya ‘026 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a first contact via structure contacting an annular top surface of a first reference electrically conductive layer that is one of the first electrically conductive layers of the first-tier alternating stack and having a top surface located above a horizontal plane including a topmost surface of the second-tier alternating stack; a first dielectric pillar structure having at least one first laterally-protruding fin portion that protrudes outward at each level of a first subset of the first electrically conductive layers that underlies the first reference electrically conductive layer; and a first-tier dielectric spacer that laterally surrounds the first contact via structure, is not in direct contact with the first dielectric pillar structure, and vertically extending through each first electrically conductive layer within a second subset of the first electrically conductive layers that overlies the first reference electrically conductive layer”.
Kang ‘590 teaches a first contact via structure (MCT; [0057]) contacting an annular top surface of a first reference electrically conductive layer (220L; [0070]) that is one of the first electrically conductive layers of the first-tier alternating stack and having a top surface located above a horizontal plane including a topmost surface of the second-tier alternating stack (see Fig. 2N);
a first dielectric pillar structure (300; [0069]) having at least one first laterally-protruding fin portion that protrudes outward at each level of a first subset of the first electrically conductive layers that underlies the first reference electrically conductive layer (see Fig. 2N); and
a first-tier dielectric spacer (304; [0068]) that laterally surrounds the first contact via structure (MCT), is not in direct contact with the first dielectric pillar structure (300), and vertically extending through each first electrically conductive layer within a second subset of the first electrically conductive layers that overlies the first reference electrically conductive layer (see Fig. 2N).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Toya ‘026 by having a first contact via structure contacting an annular top surface of a first reference electrically conductive layer that is one of the first electrically conductive layers of the first-tier alternating stack and having a top surface located above a horizontal plane including a topmost surface of the second-tier alternating stack; a first dielectric pillar structure having at least one first laterally-protruding fin portion that protrudes outward at each level of a first subset of the first electrically conductive layers that underlies the first reference electrically conductive layer; and a first-tier dielectric spacer that laterally surrounds the first contact via structure, is not in direct contact with the first dielectric pillar structure, and vertically extending through each first electrically conductive layer within a second subset of the first electrically conductive layers that overlies the first reference electrically conductive layer for the purpose of improving integration and excellent electrical characteristics (see para. [0003]) as suggested by Kang ‘590.
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Fig. 17C (Toya ‘026)
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Fig. 2N (Kang ‘590)
Regarding Claim 9, Kang ‘590 teaches a second support and contact assembly vertically extending through the first-tier alternating stack and the second-tier alternating stack and comprising:
a second contact via structure (MCT; [0057]) contacting an annular top surface of a second reference electrically conductive layer (220L; [0070]) that is one of the second electrically conductive layers of the second-tier alternating stack and having a top surface located within the horizontal plane including the topmost surface of the second-tier alternating stack (see Fig. 2N); and a second dielectric pillar structure (300; [0069]) underlying and contacting the second contact via structure (MCT), and extending into the substrate.
Allowable Subject Matter
Claims 2-8 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 2 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: “a second-tier dielectric spacer that laterally surrounds the first contact via structure, and is in contact with each of the second electrically conductive layers”. Claims 3 and 4 depend from claim 2.
Claim 5 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: “a topmost surface of the first-tier dielectric spacer contacts a bottom surface of a bottommost second insulating layer of the second insulating layers”.
Claim 6 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: “a pillar dielectric liner vertically extending through each first electrically conductive layer within the first subset of the first electrically conductive layers; and a pillar dielectric material layer laterally surrounded by the pillar dielectric liner and comprising a vertically-extending portion that vertically extends from the first contact via structure into a portion of the substrate that underlies the first-tier alternating stack; and a first dielectric fill material portion that is laterally surrounded by the pillar dielectric material layer”. Claims 7 and 8 depend from claim 6.
Claim 10 includes allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having: “the first dielectric pillar structure lacks an air gap while the second dielectric pillar structure includes an air gap; the second dielectric pillar structure comprises second laterally-protruding fin portions that protrude outward at each level of the first electrically conductive layers; and at least one additional laterally-protruding fin portion that protrudes outward at each level of a first subset of the second electrically conductive layers that underlies the second reference electrically conductive layer”. Claim 11 depends from claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Matovu et al. (US 10,269,625 B1)
Oshiki et al. (US 2018/0197874 A1)
Cui (US 9,853,038 B1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893