DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species 4, Embodiment IV, Fig. 5, item 500, claims 1-7 and 9-11, in the reply filed on January 6, 2026 is acknowledged. Claims 8 and 12-20 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (Lau) (US 2010/0213600 A1) as evidenced by or in view of Kim et al. (Kim) (US 2019/0244878 A1) in view of Upadhyayula et al. (Upadhyayula) (US 2009/0166887 A1).
In regards to claim 1, Lau (Figs. 1, 2, 4A-4F, 5 and associated text) discloses a memory device (items 100, 200, Figs. 1, 2, 4A-4F, 5) comprising: a system board (item 112) having an interface (lateral and/or bottom border/boundary/edge/surface/face/side of item 112) configured to connect to a host (not shown by Lau or the Applicant); an interposer board (item 132) directly mounted to the system board (item 112), wherein the interposer board (item 132) comprises a plurality of conductance patterns (redistribution layers, not shown, paragraph 32), each conductance pattern (redistribution layers, not shown, paragraph 32) including a cluster of contact pads (metal pads, not shown, paragraph 32); and a plurality of memory dies (items 124A, 124B, 118A, 118B) flip-chip bonded (paragraphs 38, 40) to the interposer board (item 132), wherein each memory die (items 124A, 124B, 118A, 118B) comprises memory cells. Examiner notes that is it well known by those of ordinary skill in the art that all semiconductor memory dies/chips contain individual physical memory cells for the purpose of storing or retrieving binary data (bits).
As evidenced by Kim (paragraph 27, Fig. 2A and associated text), a plurality of memory chips/die (items 11-14) can each comprise memory cells/memory cell array.
Lau as evidence by Kim does not specifically disclose wherein each memory die comprises a cluster of bump pads on a face of the memory die, wherein for each particular memory die the cluster of bump pads of the particular memory die are electrically bonded to the cluster of contact pads of one of the conductance patterns of the interposer board.
Upadhyayula (paragraphs 37, 40, 41, 46, Figs. 4-6, 12 and associated text) discloses the interposer board (item 102) comprises a plurality of conductance patterns (item 106), each conductance pattern (item 106) including a cluster of contact pads (item 108); wherein each memory die (items 116, 130) comprises a cluster of bump pads (items 118, 134) on a face of the memory die (items 116, 130), wherein for each particular memory die (items 116, 130) the cluster of bump pads (items 118, 134) of the particular memory die (items 116, 130) are electrically bonded to the cluster of contact pads (items 108) of one of the conductance patterns (items 106) of the interposer board (item 102).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Upadhyayula for the purpose of an electrical connection.
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the limitation “flip-chip bonded” has not been given patentable weight.
In regards to claim 2, Lau (Figs. 1, 2, 4A-4F, 5 and associated text) discloses wherein the plurality of memory dies (items 124A, 124B, 118A, 118B) are bare dies (paragraph 17, 20, 66, claim 3).
In regards to claim 3, Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) discloses a memory controller die (items 118A, 118B or 424) bonded to the interposer board (item 132), wherein the memory controller die (items 118A, 118B or 424) is in communication with the plurality of memory dies (items 124A, 124B, 118A, 118B) and is configured to control storage of data received on the interface of the system board (item 112) in the plurality of memory dies (items 124A, 124B, 118A, 118B).
In regards to claim 4, Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) as evidence by Kim (paragraph 27, Fig. 2A and associated text) and modified by Upadhyayula (paragraphs 37, 40, 41, 46, Figs. 4-6, 12 and associated text) discloses wherein: the memory controller die (items 118A, 118B or 424, Lau) is flip-chip bonded to the interposer board (item 132); the memory controller die (items 118A, 118B or 424, Lau, item 116, Upadhyayula) comprises a cluster of bump pads (items 118, Upadhyayula) on a face of the memory controller die (items 118A, 118B or 424, Lau, item 116, Upadhyayula); and the cluster of bump pads (items 118, Upadhyayula) of the memory controller die (items 118A, 118B or 424, Lau, item 116, Upadhyayula) are electrically bonded to the cluster of contact pads of one of the conductance patterns (redistribution layers, not shown, paragraph 32, Lau, item 106, Upadhyayula) of the interposer board (item 132, Lau, item 102, Upadhyayula).
In regards to claim 5, Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) discloses wherein: the interposer board (item 132) comprises a primary side (top side/surface) and a secondary side (bottom side/surface), the primary side (top side/surface) faces away from the system board (item 112), the secondary side (bottom side/surface) faces the system board (item 112); the memory controller die (items 118A, 118B or 424) is flip-chip bonded to the primary side (top side/surface) of the interposer board (item 132); and the memory controller die (items 118A, 118B or 424) is a bare die (paragraph 17, 20, 66, claim 3).
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the limitation “flip-chip bonded” has not been given patentable weight.
In regards to claim 6, Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) discloses a heat sink (item 102, 114 or 102 plus 114) thermally coupled to an unencapsulated top surface of the memory controller die (items 118A, 118B or 424) and thermally coupled to unencapsulated top surfaces of a set of the plurality of memory dies (items 118A, 118B) that are flip-chip bonded to the primary side of the interposer board (item 132), wherein the unencapsulated top surface of the memory controller die (items 118A, 118B or 424) and the unencapsulated top surfaces of the set of the memory dies (items 118A, 118B) face away from the system board (item 112).
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the limitation “flip-chip bonded” has not been given patentable weight.
In regards to claim 7, Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) discloses the interposer board (item 132) comprises a primary side (top side/surface) and a secondary side (bottom side/surface); and the plurality of memory dies comprise a first plurality of memory dies (items 118A, 118B) flip-chip bonded to the primary side (top side/surface) of the interposer board (item 132) and a second plurality of memory dies (items 124A, 124B) flip-chip bonded to the secondary side (bottom side/surface) of the interposer board (item 132).
The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, the limitation “flip-chip bonded” has not been given patentable weight.
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (Lau) (US 2010/0213600 A1) as evidenced by or in view of Kim et al. (Kim) (US 2019/0244878 A1) in view of Upadhyayula et al. (Upadhyayula) (US 2009/0166887 A1) as applied to claims 1-7 above, and further in view of Aleksov et al. (Aleksov) (US 2020/0006235 A1).
In regards to claim 9, Lau as evidence by Kim and modified by Upadhyayula does not specifically disclose further comprising: one or more additional interposer boards directly mounted to the system board; and additional memory dies flip-chip bonded to the one or more additional interposer boards, wherein the additional memory dies are bare dies.
Aleksov (Figs. 11A-11D and associated text) discloses one or more additional interposer boards (items 1132-1, 1132-2) directly mounted to system board (item 102); and additional memory dies (items 114-1, 114-2, 114-3, paragraph 33) bonded to the one or more additional interposer boards (items 1132-1, 1132-2).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Aleksov for the purpose of device/package density, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
Examiner takes position that Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) as evidence by Kim (paragraph 27, Fig. 2A and associated text) and modified by Upadhyayula (paragraphs 37, 40, 41, 46, Figs. 4-6, 12 and associated text) and Aleksov (Figs. 11A-11D and associated text) discloses further comprising: one or more additional interposer boards interposer boards directly mounted to system board; and additional memory dies flip-chip bonded to the one or more additional interposer boards, wherein the additional memory dies are bare dies (See rejection of claims 1 and 2 above).
In regards to claim 10, Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) as evidence by Kim (paragraph 27, Fig. 2A and associated text) and modified by Upadhyayula (paragraphs 37, 40, 41, 46, Figs. 4-6, 12 and associated text) and Aleksov (Figs. 11A-11D and associated text) discloses wherein: the system board (item 112, Lau, item 102, Upadhyayula, item 102, Aleksov) has a first major surface (top surface/side) and a second major surface (bottom surface/side); at least one of the interposer boards (item 132, Lau, items (items 1132-1, 1132-2, Aleksov) is directly mounted to the first major surface (top surface/side) but does not specifically disclose at least one of the interposer boards is directly mounted to the second major surface; and neither the interposer boards nor the system board are covered with a mold compound. Examiner notes that it is well known by those of ordinary skill in the art the interposers, packages, chips and die can be mounted to a top and bottom side/surface of a substrate/wafer/board and is just a matter of design choice and common knowledge.
It would have been obvious to modify the invention to include additional interposer boards, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include at least one of the interposer boards is directly mounted to the second major surface, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lau et al. (Lau) (US 2010/0213600 A1) as evidenced by or in view of Kim et al. (Kim) (US 2019/0244878 A1) in view of Upadhyayula et al. (Upadhyayula) (US 2009/0166887 A1) as applied to claims 1-7 above, and further in view of Seater et al. (Seater) (US 2020/0257517 A1).
In regards to claim 11, Lau (paragraphs 39, 54, Figs. 1, 2, 4A-4F, 5 and associated text) as evidenced by Kim and modified by Upadhyayula does not specifically disclose wherein the system board (item 112) comprises an M.2 board.
Seater (paragraph 24) disclose an M.2 board.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Seater for the purpose of electrical communication and having the desired circuit board.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 January 16, 2026