DETAILED ACTION
This action is responsive to the election received on 12/19/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claim(s) 1-10) in the reply filed on 12/19/2025 is acknowledged. Claim(s) 11-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Applicant’s election without traverse of Species B (Figure 10E) in the reply filed on 12/19/2025 is acknowledged. Claim(s) 7 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/21/2023, 11/03/2023, 04/17/2024, and 08/08/2025 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0352200 A1; Sano et al.; 11/2022; (“Sano”) in view of US 2022/0052073 A1; Kitazawa et al.; 02/2022; (“Kitazawa”).
Regarding Claim 1. Sano discloses A memory device (Figures 66A-B, [0333], three-dimensional memory device), comprising:
an alternating stack of insulating layers (#32, Figure 66A, insulating layers) and electrically conductive layers (#46, Figure 66A, electrically conductive layers),
a memory opening vertically extending through the alternating stack (#49’, Figures 63A and 66A, memory cavity which is filled in Figure 66A); and
a memory opening fill structure (#58, Figure 66A, memory opening fill structure) located in the memory opening (Figure 66A, #58 is located in #49’) and comprising a vertical semiconductor channel (#60, Figure 66A, vertical semiconductor channel) and a memory film (#50, Figure 66A, memory film) comprising a continuous memory material layer (#54, Figure 66A, memory material layer) which continuously extends through the entire alternating stack (Figure 66A, #54 continuously extends through the entire alternating stack).
Sano does not disclose that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner. However, Sano does teach that during the method of formation (Figures 59A-66B) that second/sacrificial material layers (#42, Figure 59C), made of a silicon/germanium material (see [0123], “sacrificial material layers 42 can be spacer material layers that comprise . . . a semiconductor material including at least one of silicon and germanium”) are removed via etching (see [0304]) selective to (i.e. avoiding etching) the first/insulating material layers (#32, Figure 59D), made of silicon nitride (see [0121], “Insulating materials that can be employed for the insulating layers 32 include, but are not limited to . . . silicon nitride”) to make space for formation of the electrically conductive layers (#46, Figure 61A).
Kitazawa teaches a semiconductor memory structure (Figures 19F and 20) comprising an alternating stack of insulating layers (#136, Figure 20) and electrically conductive layers (#146, Figure 20), wherein a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner (#34s, Figure 19F, each #146 is in contact with an underlying and an overlying dielectric barrier liner made of silicon oxycarbide according to [0165]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the silicon oxycarbide liners of Kitazawa on the upper and lower surfaces of the electrically conductive layers of Sano. The liners are provided to improve the protection of silicon nitride layers during etching of silicon/germanium layers during formation of the alternating stack (see [0196] of Kitazawa, “second sacrificial material layers 141 include silicon nitride . . . first sacrificial material layers 131 include a silicon-germanium alloy . . . dielectric barrier liners 34, such as silicon oxycarbide liners protect the second sacrificial material layers 141 from being etched during the isotropic etch process” and Figures 17-19D).
Regarding Claim 2. Sano in view of Kitazawa disclose The memory device of Claim 1, wherein the memory film (Sano, #50) comprises, from outside to inside, a dielectric metal oxide blocking dielectric layer (Sano, #5A, Figure 66B, dielectric metal oxide blocking layer), a silicon oxide blocking dielectric layer (Sano, #5B, Figure 66B, silicon oxide blocking dielectric layer), the continuous memory material layer (Sano, #54, Figure 66A, memory material layer), and a tunneling dielectric layer (Sano, #56, Figure 66B, tunneling dielectric layer).
Regarding Claim 3. Sano in view of Kitazawa disclose The memory device of Claim 1, wherein the first electrically conductive layer (Sano, upper #46, Figure 66B) comprises:
an upper annular protrusion portion (Figure 46, the #46L layer of #46 includes an upper protrusion portion near #55 which is annular in shape as it forms a ring or annular shape around the memory core according to [0365]) that protrudes above a first horizontal plane including an interface between the first electrically conductive layer and the overlying silicon oxycarbide liner (Sano in view of Kitazawa, Figure 66B of Sano shows that the upper protrusion extends above an interface of #46 and upper #32, incorporation of the silicon oxycarbide liners of Kitazawa into the conductive layer structure #46 of Sano, as proposed in claim 1, would result in the protrusion extending above an interface of the upper silicon oxycarbide liner and #46); and
a lower annular protrusion portion (Figure 46, the #46L layer of #46 includes a lower protrusion portion near #55 which is annular in shape as it forms a ring or annular shape around the memory core according to [0365]) that protrudes below a second horizontal plane including an interface between the first electrically conductive layer and the underlying silicon oxycarbide liner (Sano in view of Kitazawa, Figure 66B of Sano shows that the lower protrusion extends below an interface of #46 and lower #32, incorporation of the silicon oxycarbide liners of Kitazawa into the conductive layer structure #46 of Sano, as proposed in claim 1, would result in the protrusion extending below an interface of the lower silicon oxycarbide liner and #46).
Regarding Claim 4. Sano in view of Kitazawa disclose The memory device of Claim 3, wherein:
the upper annular protrusion portion contacts a sidewall of an opening in the overlying silicon oxycarbide liner (Sano in view of Kitazawa, Figure 66B of Sano shows that the upper protrusion extends above an interface of #46 and #32, the silicon oxycarbide liners (#34) of Kitazawa extend along the entire length of the electrically conductive layers until an opening for the memory structure (see Figure 19F of Kitazawa), incorporation into Sano would result in the protrusion extending along a sidewall of the silicon oxycarbide layers);
the lower annular protrusion portion contacts a sidewall of an opening in the underlying silicon oxycarbide liner (Sano in view of Kitazawa, Figure 66B of Sano shows that the lower protrusion extends below an interface of #46 and #32, the silicon oxycarbide liners (#34) of Kitazawa extend along the entire length of the electrically conductive layers until an opening for the memory structure (see Figure 19F of Kitazawa), incorporation into Sano would result in the protrusion extending along a sidewall of the silicon oxycarbide layers); and
the memory opening fill structure vertically extends through the opening in the overlying silicon oxycarbide liner and through the opening in the underlying silicon oxycarbide liner (Kitazawa, Figure 19F, the memory opening fill structure #55 extends through the opening in the #34s).
Regarding Claim 5. Sano in view of Kitazawa disclose The memory device of Claim 3, wherein:
the upper annular protrusion portion comprises a first inner annular convex surface (Sano, Figure 66B annotated below, #IACS of the upper protrusion which is convex away from the memory opening and an annular ring shape around the memory core) and a first outer cylindrical surface (Sano, Figure 66B annotated below, #OCS of the upper protrusion which is a cylindrical outer surface away from the memory opening and wrapping around the memory core); and
the lower annular protrusion portion comprises a second inner annular convex surface (Sano, Figure 66B annotated below, #IACS of the lower protrusion which is convex away from the memory opening and an annular ring shape around the memory core) and a second outer cylindrical surface (Sano, Figure 66B annotated below, #OCS of the lower protrusion which is a cylindrical outer surface away from the memory opening and wrapping around the memory core).
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Regarding Claim 6. Sano in view of Kitazawa disclose The memory device of Claim 1, wherein the memory film further comprises a vertical stack of tubular silicon oxide spacers (#134/#234, Figures 66A and 66B, tubular dielectric spacers) in contact with a respective one of the insulating layers (Figure 66B, each #134/#234 is observed to be in direct contact with a #32).
Regarding Claim 9. Sano in view of Kitazawa disclose The memory device of Claim 1, wherein:
the overlying silicon oxycarbide liner is in contact with a bottom surface of an overlying insulating layer of the insulating layers (Sano in view of Kitazawa, Sano Figure 66B, incorporation of the silicon oxycarbide liners of Kitazawa, observed to be between the electrically conductive layers and the insulating layers, into the structure of Sano, as proposed in claim 1, would result in the upper silicon oxycarbide layer contacting the bottom surface of the overlying #32);
the underlying silicon oxycarbide liner is in contact with a top surface of an underlying insulating layer of the insulating layers (Sano in view of Kitazawa, Sano Figure 66B, incorporation of the silicon oxycarbide liners of Kitazawa, observed to be between the electrically conductive layers and the insulating layers, into the structure of Sano, as proposed in claim 1, would result in the lower silicon oxycarbide layer contacting the upper surface of the underlying #32); and
the insulating layers do not embed a seam or an airgap therein (Sano, Figure 66A, #32s do not embed an air gap or seam within themselves).
Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0352200 A1; Sano et al.; 11/2022; (“Sano”) in view of US 2022/0052073 A1; Kitazawa et al.; 02/2022; (“Kitazawa”).
Regarding Claim 1. Sano discloses A memory device (Figure 17, [0185], memory die), comprising:
an alternating stack of insulating layers (#32, Figure 17, insulating layers) and electrically conductive layers (#46, Figure 17, electrically conductive layers),
a memory opening vertically extending through the alternating stack (#49, Figure 4A, memory opening which is filled in Figure 17); and
a memory opening fill structure (#58, Figure 17, memory opening fill structure) located in the memory opening (Figure 17, #58 is located in #49) and comprising a vertical semiconductor channel (#60, Figure 13B, vertical semiconductor channel) and a memory film (#50, Figure 13B, memory film) comprising a continuous memory material layer (#54, Figure 13B, memory material layer) which continuously extends through the entire alternating stack (Figure 13B, #54 continuously extends through the entire alternating stack).
Sano does not disclose that a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner. However, Sano does teach that during the method of formation (Figures 6A-16A) that second/sacrificial material layers (#42, Figure 6A), which may be made of a silicon/germanium material (see [0123], “sacrificial material layers 42 can be spacer material layers that comprise . . . a semiconductor material including at least one of silicon and germanium”) are removed via etching (see [0145]) selective to (i.e. avoiding etching) the first/insulating material layers (#32, Figure 7), made of silicon nitride (see [0121], “Insulating materials that can be employed for the insulating layers 32 include, but are not limited to . . . silicon nitride”) to make space for formation of the electrically conductive layers (#46, Figure 17).
Kitazawa teaches a semiconductor memory structure (Figures 19F and 20) comprising an alternating stack of insulating layers (#136, Figure 20) and electrically conductive layers (#146, Figure 20), wherein a first electrically conductive layer of the electrically conductive layers is in contact with an underlying silicon oxycarbide liner and with an overlying silicon oxycarbide liner (#34s, Figure 19F, each #146 is in contact with an underlying and an overlying dielectric barrier liner made of silicon oxycarbide according to [0165]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the silicon oxycarbide liners of Kitazawa on the upper and lower surfaces of the electrically conductive layers of Sano. The liners are provided to improve the protection of silicon nitride layers during etching of silicon/germanium layers during formation of the alternating stack (see [0196] of Kitazawa, “second sacrificial material layers 141 include silicon nitride . . . first sacrificial material layers 131 include a silicon-germanium alloy . . . dielectric barrier liners 34, such as silicon oxycarbide liners protect the second sacrificial material layers 141 from being etched during the isotropic etch process” and Figures 17-19D).
Regarding Claim 10. Sano in view of Kitazawa disclose The memory device of Claim 1, wherein each of the electrically conductive layers has a respective uniform vertical thickness throughout (Sano, [0148], “each backside recess 43 can have a uniform height throughout” wherein the backside recesses #43 are where the electrically conductive layers #46. Figure 17, are formed, i.e. #46s may has a uniform vertical thickness, or height, throughout).
Allowable Subject Matter
Claim(s) 8 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the cited prior art, either alone or in combination, teaches “the memory opening fill structure further comprises divot-fill annular dielectric spacers; and each tubular silicon oxide spacer is in contact with a respective overlying one of the divot-fill annular dielectric spacers and is in contact with a respective underlying one of the divot-fill annular dielectric spacers” as recited in claim 8, and in combination with all of the other required limitations of the claim.
Regarding Claim 8. Sano in view of Kitazawa disclose The memory device of Claim 6.
Sano in view of Kitazawa do not disclose the memory opening fill structure further comprises divot-fill annular dielectric spacers; and each tubular silicon oxide spacer is in contact with a respective overlying one of the divot-fill annular dielectric spacers and is in contact with a respective underlying one of the divot-fill annular dielectric spacers. No other prior art was identified which teaches this limitation and/or provides motivation to form the recited structures in a related memory device. Therefore claim 8 is interpreted to contain allowable subject matter and would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2018/0040627 A1; Kanakamedala et al.; 02/2018 – Figure 11D discloses a memory device comprising an alternating stack of electrically conductive layers (#46) and insulating layers (#32), and a dielectric liner structure (#44) on upper and lower surfaces of the electrically conductive layers (#46), and each electrically conductive layer has protrusions on the upper and lower surface to modify the gate length [0164].
US 2022/0352199 A1; Mukae et al.; 11/2022 – Figures 66A-66B disclose a memory device comprising an alternating stack of electrically conductive layers (#46) and insulating layers (#32), and each electrically conductive layer has protrusions on the upper and lower surface to modify the gate length ([0314]).
US 2022/0352201 A1; Hinoue et al.; 11/2022 – Figures 66A-66B disclose a memory device comprising an alternating stack of electrically conductive layers (#46) and insulating layers (#32), and each electrically conductive layer has protrusions on the upper and lower surface to modify the gate length ([0314]).
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/TYLER J WIEGAND/Examiner, Art Unit 2812