Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, (claims 1-15), in the reply filed on 11/26/2025 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/26/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20170352681 A1; hereinafter “Lee”) in view of Kitazawa et al. (US 20220052073 A1; hereinafter “Kitazawa”) (Kitazawa has been listed in the 04/17/2024 IDS).
In re claim 1, Lee discloses in fig. 4, a memory device 10c (¶7-8, 59), comprising:
an alternating stack 54 of insulating layers 52 and electrically conductive layers 50 (¶37), wherein a first electrically conductive layer of the electrically conductive layers 55 (¶38) has a first major horizontal surface (e.g., an upper surface of the conductive layer 55; hereinafter “S1”) in contact with a liner 80 (¶59) and an opposing second major surface (e.g., a lower surface of the conductive layer 55; hereinafter “S2”) in contact with one of the insulating layers 52 or with a dielectric material layer composed of a silicon oxide material;
a memory opening 33 vertically extending through the alternating stack 54 (¶23; the label of the memory opening 33 is shown in fig. 1); and
a memory opening fill structure located in the memory opening 33 and comprising a vertical semiconductor channel 56 and a memory film 60 (¶43, 46).
Lee discloses the liner 80 comprises silicon dioxide (¶59). However, Lee does not expressly disclose the liner is a silicon oxycarbide liner.
In the same field of endeavor, Kitazawa discloses a memory device (figs. 14A-14H), comprising: a dielectric liner 34 in contact with a conductive layer 146 (¶211), wherein the dielectric liner 34 is made of silicon oxycarbide (¶165).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to form the liner made of silicon oxycarbide in the memory device of Lee to incorporate a low dielectric constant liner and enhance etch resistance (¶165 of Kitazawa).
In re claim 2, Lee, as modified by Kitazawa, discloses memory device of Claim 1 outlined above.
Lee further discloses in fig. 4, wherein the memory film comprises, from outside to inside, a dielectric metal oxide blocking dielectric layer 42 (¶30), a silicon oxide blocking dielectric layer 40 (¶28), a memory material layer 38 (¶27), and a dielectric layer 36 (¶25-26).
Lee does not expressly disclose the memory material layer is a continuous material layer and dielectric layer 36 is a tunneling dielectric layer.
Kitazawa further discloses that a memory film (memory film 150', Fig. 14H) comprises, a continuous memory material layer (charge storage layer 24, see Fig. 14H), and
a tunneling dielectric layer (tunneling dielectric layer 26, Fig. 14H).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kitazawa into the memory device of Lee to enhance memory storage and maintain reliability for writing and storing date.
In re claim 3, Lee, as modified by Kitazawa, discloses memory device of Claim 2 outlined above.
Lee further discloses in fig. 4, wherein each of the electrically conductive layers 52 is in direct contact with a respective surface segment of an outer sidewall of the dielectric metal oxide blocking dielectric layer 42.
Allowable Subject Matter
Claims 10-15 are allowed.
Claims 4-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, closest prior art of record, alone or in combination, does not expressly disclose a memory device including a vertical stack of tubular silicon oxide spacers that are vertically spaced apart from each other, and laterally surrounding and contacting the dielectric metal oxide blocking dielectric layer; and divot-fill annular dielectric spacers contacting a concave tapered surface of a respective one of the tubular silicon oxide spacers and contacting a respective cylindrical surface segment of an outer sidewall of the dielectric metal oxide blocking dielectric layer.
Claims 5-7 are indicated allowable based on their dependency on claim 4.
Regarding claim 8, closest prior art of record, alone or in combination, does not expressly disclose a memory device including the first electrically conductive layer comprises a first convex and tapered annular surface segment having a first radius of curvature, and a second convex and tapered annular surface segment having a second radius of curvature that is less than the first radius of curvature; and an edge of the second convex and tapered annular surface segment is adjoined to an edge of the horizontally-extending planar surface.
Regarding claim 9, closest prior art of record, alone or in combination, does not expressly disclose a memory device including all the details of the silicon oxycarbide liners in the first tier and second tier.
Regarding claim 10, Kitazawa discloses in fig. 35, a memory device, comprising:
an alternating stack of insulating layers 236 and electrically conductive layers 146 (¶322, 319),
wherein each of the electrically conductive layers 146 is vertically spaced from a respective overlying insulating layer 236 and from a respective underlying insulating layer 236 by a respective backside dielectric metal oxide blocking dielectric layer 44 (¶316),
wherein a first backside dielectric metal oxide blocking dielectric layer of the backside dielectric metal oxide blocking dielectric layers comprises a second horizontal surface (e.g., a lower horizontal surface of 44) that is in direct contact with one of the insulating layers 236 or a dielectric material layer composed of a silicon oxide material;
a memory opening 49 vertically extending through the alternating stack 236, 146 (the memory opening 49 is shown in one of the earlier figure, i.e., Fig. 31C. ¶84); and
a memory opening fill structure 55 located in the memory opening 49 (¶114) and comprising a vertical semiconductor channel 60 (¶114) and a memory film 250 (¶289).
Kitazawa discloses in another embodiment, e.g., in fig. 25, wherein a first backside dielectric metal oxide blocking dielectric layer of the backside dielectric metal oxide blocking dielectric layers 121 (¶199) comprises a first horizontal surface that is in direct contact with a silicon oxycarbide liner 34 (¶165). However, in this embodiment, the second horizontal surface of the first backside dielectric metal oxide blocking dielectric layer is also in contact with another silicon oxycarbide liner 34. It would not have been obvious to one of ordinary skill in the art to modify these two embodiments and arrive at the claimed invention.
Therefore, Kitazawa does not discloses all the limitations of claim 10 including wherein a first backside dielectric metal oxide blocking dielectric layer of the backside dielectric metal oxide blocking dielectric layers comprises a first horizontal surface that is in direct contact with a silicon oxycarbide liner and a second horizontal surface that is in direct contact with one of the insulating layers or a dielectric material layer composed of a silicon oxide material.
Claims 11-15 are indicated allowable based on their dependency on claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893
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