Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Sun (WO 2019/192376, hereinafter Sun) in view of Shi (WO 2011/008665, hereinafter Shi).
With respect to claim 1, Sun discloses am image sensing device (Fig. 7) comprising: a substrate (10); a first dielectric layer (31) formed over the substrate; and a passivation layer (32 – high K dielectric layer. e.g. HfO) formed over the first dielectric layer, wherein the first dielectric layer directly contacts the field effect passivation layer (31 directly contacts 32).
Sun does not explicitly disclose that the passivation layer is a field effect passivation layer.
In an analogous art, Shi discloses that the passivation layer is a field effect passivation layer (Para 0024 – HFO2 works as a passivation layer for field effect transistor). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Sun’s device by having Shi’s disclosure in order to reduce surface defects in a semiconductor device.
With respect to claim 3, Sun discloses wherein the first dielectric layer includes SiO₂ (Page 08 – Para 01 – silicon oxide).
With respect to claim 4, Sun discloses wherein the first high-k dielectric layer includes Al₂O₃ (Page 07, last para – Aluminum oxide).
With respect to claim 5, Sun discloses wherein the second high-k dielectric layer includes HfO₂ (Page 07, last para – hafnium oxide).
With respect to claim 6, Sun discloses wherein the second dielectric layer includes SiO₂ (Page 08 – Para 01 – silicon oxide).
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sun/Shi in view of Ma et al. (US 6,407,435, hereinafter Ma).
With respect to claim 2, Sun/Shi discloses the image sensing device of claim 1.
Sun/Shi does not explicitly disclose wherein the field effect passivation layer comprises: a first high-k dielectric layer formed over the first dielectric layer and having a first dielectric constant higher thana dielectric constant of the first dielectric layer; a second high-k dielectric layer having a second dielectric constant higher than the dielectric constant of the first dielectric layer; and a second dielectric layer formed between the first high-k dielectric layer and the second high-k dielectric layer.
In an analogous art, Ma discloses wherein the field effect passivation layer comprises: a first high-k dielectric layer (140 of Fig. 3) formed over the first dielectric layer (130) and having a first dielectric constant higher thana dielectric constant of the first dielectric layer (Col. 4; lines 35-45); a second high-k dielectric layer having a second dielectric constant higher than the dielectric constant of the first dielectric layer
(Col. 4; lines 40-55; layer stack can be repeated many times); and a second dielectric layer (150) formed between the first high-k dielectric layer and the second high-k dielectric layer. (Page 04; lines 40-55)
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Sun/Shi’s device by having Ma’s disclosure in order to reduce tunneling current to improve the performance of a semiconductor device.
With respect to claim 7, Sun/Shi does not explicitly disclose wherein each of the first dielectric layer, and the second dielectric layer has a thickness ranging from 20 A to 100 A.
In an analogous art, Ma discloses wherein each of the first dielectric layer, and the second dielectric layer has a thickness ranging from 20 A to 100 A (Col. 3; line 65- Col.; line 5).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Sun/Shi’s device by having Ma’s disclosure in order to reduce tunneling current to improve the performance of a semiconductor device.
Claims 8-9, 11-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ma.
With respect to claim 8, Ma discloses: a substrate (112 of Fig. 3); a first dielectric layer (130) formed over the substrate; a first high-k dielectric layer (140) formed over the first dielectric layer and having a first dielectric constant higher than a dielectric constant of the first dielectric layer (Col. 4; lines 35-45); a second dielectric layer (150) formed over the first high-k dielectric layer, wherein the first dielectric layer directly contacts the first high-k dielectric layer (130 directly contacts 140).
Ma does not explicitly disclose a second high-k dielectric layer formed over the second dielectric layer and having a second dielectric constant higher than the dielectric constant of the first dielectric layer; a third dielectric layer formed over the second high-k dielectric layer; and a third high-k layer formed over the third dielectric layer and having a third dielectric constant higher than a reference dielectric constant.
In another embodiment, Ma discloses a second high-k dielectric layer formed over the second dielectric layer and having a second dielectric constant higher than the dielectric constant of the first dielectric layer (Col. 4; lines 40-55; layer stack can be repeated many times); a third dielectric layer formed over the second high-k dielectric layer; and a third high-k formed over the third dielectric layer and having a third dielectric constant higher than a reference dielectric constant (Page 04; lines 40-55 – dielectric layers and high-k dielectric layers repeat).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ma’s first embodiment by having disclosure from second embodiment in order to reduce tunneling current to improve the performance of a semiconductor device.
With respect to claim 14, Ma discloses:
forming a first dielectric layer (130 of Fig. 3) over a substrate (112); forming a first high-k dielectric layer (140) having a first dielectric constant higher than a dielectric constant of the first dielectric layer over the first dielectric layer (Col. 4; lines 35-45); forming a second dielectric layer (150) over the first high-k dielectric layer, wherein the first dielectric layer directly contacts the first high-k dielectric layer (130 directly contacts 140).
Ma does not explicitly disclose forming a second high-k dielectric layer having a second dielectric constant higher than the dielectric constant of the first dielectric layer over the second dielectric layer.
In another embodiment, Ma discloses forming a second high-k dielectric layer having a second dielectric constant higher than the dielectric constant of the first dielectric layer over the second dielectric layer (Col. 4; lines 40-55; layer stack can be repeated many times). Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ma’s first embodiment by having disclosure from second embodiment in order to reduce tunneling current to improve the performance of a semiconductor device.
With respect to claims 9, and 15, Ma discloses wherein each of the first dielectric layer, the second dielectric layer, and the third insulating layer includes SiO2 (Col.4; lines 30-36 – first dielectric layer130 comprises of SiO2-seond and third dielectric layers are repetition of 130).
With respect to claims 11, and 17, Ma discloses wherein the second high-k dielectric layer includes HfO2 (Col. 4; lines 35-40).
With respect to claims 12, Ma discloses wherein the third dielectric layer includes ZrOo (Col. 4; lines 35-45).
With respect to claim 13, Ma discloses wherein each of the first dielectric layer, the second 25 dielectric layer, and the third insulating layer have a thickness ranging from 20 A to 100 A (Col. 3; line 65- Col.; line 5).
Claims 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Chen et al. (US 2018/0166476, hereinafter Chen).
With respect to claims 10, and 16, Ma does not explicitly disclose wherein the first high-k dielectric layer includes Al2O3.
In an analogous art, Chen discloses wherein the first high-k dielectric layer includes Al2O3 (Para 0016 & 0026).
Therefore, it would have been obvious to one of an ordinary skilled in the art at the time of invention to modify Ma’s device/method by having Chen’s disclosure in order to improve the insulating properties of a semiconductor device.
Response to Arguments
Applicant's arguments filed 04/08//2026 have been considered, however they are not persuasive.
Based on new ground of rejection, applicant’s arguments regarding amended claims are moot.
Regarding amended claims 8 & 14, applicant argues that prior art does not explicitly disclose the amended limitations. Examiner respectfully disagrees because
Ma clearly discloses wherein the first dielectric layer directly contacts the first high-k dielectric layer (Fig. 3 - 130 directly contacts 140). Therefore, the rejection has been maintained.
Allowable Subject Matter
Claims 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 18, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the first dielectric layer directly contacts an upper surface of the substrate and a lower surface of the field effect passivation layer, wherein the substrate comprises a first portion and a second portion recessed in a thickness direction to define a groove, wherein the first dielectric layer extends over an upper surface of the first portion, inner side surfaces of the first portion defining the groove, and an upper surface of the second portion, and wherein the field effect passivation layer is disposed within the groove in direct contact with the first dielectric layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 19, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the first dielectric layer directly contacts an upper surface of the substrate and a lower surface of the first high-k dielectric layer, wherein a field effect passivation layer comprises the first high-k dielectric layer, the second dielectric layer, the second high-k dielectric layer, the third dielectric layer, and the third high-k dielectric layer, wherein the substrate comprises a first portion and a second portion recessed in a thickness direction to define a groove,
wherein the first dielectric layer extends over an upper surface of the first portion, inner side surfaces of the first portion defining the groove, and an upper surface of the second portion, and wherein the field effect passivation layer is disposed within the groove in direct contact with the first dielectric layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 20, none of the prior art on record disclose or render obvious the claimed limitations including “wherein the first dielectric layer directly contacts an upper surface of the substrate and a lower surface of the first high-k dielectric layer, wherein a field effect passivation layer comprises the first high-k dielectric layer the second dielectric layer, the second high-k dielectric layer, wherein the substrate comprises a first portion and a second portion recessed in a thickness direction to define a groove, wherein the first dielectric layer extends over an upper surface of the first portion, inner side surfaces of the first portion defining the groove, and an upper surface of the second portion, and wherein the field effect passivation layer is disposed within the groove in direct contact with the first dielectric layer” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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