DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species-II in the reply filed on 02/11/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-18 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over YOO; Hyangkeun (US PGpub: 2019/0348539 A1), herein after YOO, in view of YOO.
Regarding claim 12, YOO teaches an ambipolar transistor comprising:
a substrate (101 (FIG. 1B));
an insulating film formed on the substrate (110);
a first electrode (source electrode on top of source region 170) and a second electrode (drain electrode on top of drain region 180) located on the insulating film (110) ;
a channel part (1010 along with 170 and 180) located on the insulating film and connected between the first electrode and the second electrode, and including a first channel doped with a first type and a second channel doped with a second type (1010 is doped with p-type and 170 and 180 doped with n-type or vice-versa in Paragraph [0039]); and
a first ferroelectric pattern and a second ferroelectric pattern (plurality of channel part 120b) located on at least the channel part ; and
a gate (155) located above the first ferroelectric pattern and the second ferroelectric pattern.
YOO does not explicitly teach first and second ferroelectric layer.
However, YOO teaches, in different embodiment, first (140, FIG. 8B) and second ferroelectric layer (1200).
Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use YOO’s ambipolar transistor with ferroelectric layer teaching from YOO in order to produce a ferroelectric semiconductor device capable of improving the reliability of the ferroelectric polarization switching operation.
Regarding claim 13, YOO teaches the ambipolar transistor of claim 12, further comprising an insulating layer (110) configured to insulate at least the first ferroelectric pattern and the second ferroelectric pattern, and the channel part (Paragraph [0027]).
Regarding claim 14, YOO teaches the ambipolar transistor of claim 13, wherein the insulating layer (110) insulates the gate and the channel part.
Regarding claim 15, YOO teaches, in view of YOO, the ambipolar transistor of claim 12, wherein: a projection of the first ferroelectric pattern (1200, FIG. 8B) in a direction of the substrate overlaps at least portions of projections of the first and second channels (1010 and 170, 180 in FIG. 1B) in the direction of the substrate (101); and a projection of the second ferroelectric pattern (140) in the direction of the substrate overlaps at least portions of the projections of the first and second channels in the direction of the substrate (see FIG. 1B and 8B, both ferroelectric layer overlaps first and second channel in the direction of substrate).
Regarding claim 16, YOO teaches the ambipolar transistor of claim 12, wherein: the first channel and the second channel are spaced apart from each other (1010 and 170 or 180 (1B) are spaced apart in FIG. 8B); the first channel is a semiconductor doped with an N type; and the second channel is a semiconductor doped with a P type (Paragraph [0039]).
Regarding claim 17, YOO teaches the ambipolar transistor of claim 12, wherein: the channel part is a semiconductor; the first channel is a region where a portion of the channel part is doped with an N type; the second channel is a region where another portion of the channel part is doped with a P type; (Paragraph [0039]) and the first channel and the second channel are located in the same semiconductor (Paragraph [0039]-[0043]).
Regarding claim 18, YOO teaches the ambipolar transistor of claim 12, wherein: each of the gate electrode, the first electrode, and the second electrode includes any one or more of a semiconductor, metal, gold (Au), chromium (Cr), titanium (Ti), titanium nitride (TiN), palladium (Pd), and platinum (Pt) (Paragraph [0038], source electrode and drain electrode is also known to use material contained in the list); and each of the first ferroelectric pattern and the second ferroelectric pattern includes any one or more of ferroelectric organic materials including any one or more of HZO(Zr:HfO2), Al:HfO2, Si:HfO2 P(VDF-TrFE) (poly (vinylidenefluoride- co-trifluoroethylene), polyvinylidene fluoride (PVDF), polytrifluoroethylene, odd- numbered nylon, and ferroelectric inorganic materials including any one or more of PZT, BaTiO3, and PbTiO3 (Paragraph [0033]).
Regarding claim 22, YOO teaches the ambipolar transistor of claim 12, wherein the substrate is any one of a glass substrate and a semiconductor substrate (Paragraph [0022]).
Claims 23 are rejected under 35 U.S.C. 103 as being unpatentable over YOO; Hyangkeun (US PGpub: 2019/0348539 A1), herein after YOO, in view of YOO and in further view of Suzuki et al. (US PGpub: 2008/0169349 A1), herein after Suzuki.
Regarding claim 23, YOO does not explicitly teaches the ambipolar transistor of claim 12, further comprising a spacer formed on a side surface of the gate.
However, Suzuki teaches a spacer formed on a side surface of the gate ( A sidewall (side wall spacer) 1308 is formed on a side surface of the gate electrode 1304, FIG. 16A) in order to insulate the gate.
Claims 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over YOO; Hyangkeun (US PGpub: 2019/0348539 A1), herein after YOO, in view of YOO and in further view of PARK et al. (US PGpub: 2020/0342300 A1), herein after PARK.
Regarding claim 19, YOO teaches in view of PARK the ambipolar transistor of claim 12, wherein: a dipole control signal and a gate signal are provided to the gate(This is known to people skilled in the art as in PARK et al. (US PGpub: 2020/0342300 A1) in Paragraph [0032] in order to improve the ability to store and read different signal information); the dipole control signal is a pulse train (gate signal is provided on gate electrode); and the channel control signal is a direct current signal (Paragraph [0042], [0043], as for example, holes can be induced in the channel layer 102 from the channel structure 1010, or electrons ejected from the channel layer 102).
Regarding claim 20, YOO teaches in view of PARK the ambipolar transistor of claim 19, wherein the dipole control signal controls directions of dipoles formed in the first ferroelectric pattern and the first ferroelectric pattern, and controls a polarity change characteristic of the dipoles using any one or more of an amplitude, a pulse width, a duty ratio, and the number of pulses of the pulse train in PARK in Paragraph [0032] in order to improve the ability to store and read different signal information.
Regarding claim 21, YOO teaches in view of PARK the ambipolar transistor of claim 19, wherein an amplitude of the dipole control signal is greater than a magnitude of the channel control signal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHEIKH MARUF/Primary Examiner, Art Unit 2897