DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 13 and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11, line 21 recites “the control high concentration regions”. No control high concentration regions have been claimed in this claim or in any claim from which it depends. This renders the claim indefinite.
Claim 13, line 6 recites “the P-type second control base region”. The second control base region is claimed in claim 4 from which this claim depends as an N-type region. It is thus unclear what the P-type second control base region is intended to be.
Claim 23, line 16 recites “the P type control base region”. The control base region is claimed earlier in the claim as an N type region. It is thus unclear what the P type control base region is intended to be.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KOEPP (US 20160268423).
Regarding claim 1, KOEPP discloses a semiconductor device comprising:
a semiconductor substrate (the substrate 100 for circuit 2 including devices 1 and 3, see fig 1-4, para 57 and 39) including an upper surface (the upper surface of 100, see fig 1-4) and a lower surface (the lower surface of 100, see fig 1-4) and containing silicon carbide (the substrate 100 can be SiC, see para 39 and 29); and
a control circuit unit (the device 1 formed in 2, see fig 1-4, para 35) formed in the semiconductor substrate and including at least a first control element (the element of 1 whose cross-section is shown in fig 2, see para 39) comprising:
a first control source region provided in the upper surface of the semiconductor substrate (source region 201, see fig 2, para 35);
a first control drain region (drain region 205, see fig 2, para 35) provided in the upper surface of the semiconductor substrate and being of a same conductivity type as the first control source region (201 and 205 are both of the first conductivity type, see para 35);
a first control base region (fig 1-4, 225, para 39) provided in contact with the first control source region (225 is in direct contact with 201, see fig 2) and being of a different conductivity type from the first control source region (225 an be p-type, see para 39); and
a first control gate trench section (the trench containing 271, 270 and 210 in the cross-section in fig 2, see fig 1-2, para 35) provided from the upper surface of the semiconductor substrate to an internal portion of the semiconductor substrate (the trench extends from the top of 100 to 15, see fig 2) and being in contact with the first control base region (271 is in direct contact with 225, see fig 2),
wherein the first control source region and the first control drain region are N type regions (201 and 205 can be n-type, see para 35),
the first control base region is a P type region provided below the first control source region (225 can be p-type and extends below 201, see fig 2, para 39),
an N type first control drift region (n-type region 15, see fig 2, para 39) connects the first control base region to the first control drain region (a line can be drawn from 225 under 201 through 15 under the gate trenches to 205, see fig 2),
the first control gate trench section is in contact with the first control base region, from a boundary between the first control source region and the first control base region to a boundary between the first control drift region and the first control base region (271 is in direct contact with 225 from the border between 201 and 225 to the border between 15 and 225, see fig 2),
the first control drift region extends under the first control source region and the first control drain region (15 extends under 201 and 205, see fig 2), and
the first control base region is disposed between the first control source region and the first control drift region in a depth direction of the semiconductor substrate (225 is between 201 and 15 in the vertical direction, see fig 2).
Regarding claim 2, KOEPP discloses the semiconductor device according to claim 1, further comprising:
a power element unit (device 3 that can be a vertical power transistor, see fig 1-4, para 57) that is formed in the semiconductor substrate (2 and 3 are formed in the same substrate, see fig 4) and controls whether to cause a current to flow between the upper surface and the lower surface of the semiconductor substrate (the device and the channel 35 is vertical, see fig 4, para 58),
wherein
the power element unit includes: a power source region provided in the upper surface of the semiconductor substrate (fig 4B, 401, para 58);
a power drain region provided in the lower surface of the semiconductor substrate and being of a same conductivity type as the power source region (401 and 409 are the source and drain regions of a single transistor, see fig 4, 409, para 58);
a power base region provided below the power source region and being of a different conductivity type from the power source region (402 is the base region of the transistor that includes 401 and 409, see fig 4B, para 58);
a power drift region provided between the power base region and the power drain region and being of a same conductivity type as the power source region (406 is the drift region of the transistor including 401, 409 and 402, see fig 4B, para 58); and
a power gate trench section (the trench gate comprising 403, 405, 407 and 408, see fig 4B, para 58) provided from the upper surface of the semiconductor substrate to such a depth as to reach the power drift region and being in contact with the power base region (see fig 4B), and
the control circuit unit controls an operation of the power element unit (the second transistor 122 can be the lateral transistor of fig 1 and is connected to the first transistor 121 which can be the vertical transistor of fig 4B, see fig 12, para 89).
Regarding claim 22, KOEPP discloses the semiconductor device according to claim 1, further comprising:
a power element unit (device 3 that can be a vertical power transistor, see fig 1-4, para 57) that is formed in the semiconductor substrate (2 and 3 are formed in the same substrate, see fig 4) and controls whether to cause a current to flow between the upper surface and the lower surface of the semiconductor substrate (the device and the channel 35 is vertical, see fig 4, para 58), wherein
the power element unit includes: a power source region provided in the upper surface of the semiconductor substrate (fig 4B, 401, para 58);
a power drain region provided in the lower surface of the semiconductor substrate and being of a same conductivity type as the power source region (401 and 409 are the source and drain regions of a single transistor, see fig 4, 409, para 58);
a power base region provided below the power source region and being of a different conductivity type from the power source region (402 is the base region of the transistor that includes 401 and 409, see fig 4B, para 58);
a power drift region provided between the power base region and the power drain region and being of a same conductivity type as the power source region (406 is the drift region of the transistor including 401, 409 and 402, see fig 4B, para 58); and
a pair of power gate trench sections (a pair of the trench gate comprising 403, 405, 407 and 408, see fig 4B, para 58) provided from the upper surface of the semiconductor substrate to such a depth as to reach the power drift region and being in contact with the power base region (see fig 4B),
wherein the power base region and the power source region are disposed between the pair of power gate trench sections (401 and 402 are between trenches 408, see fig 4B),
the control circuit unit controls an operation of the power element unit (the second transistor 122 can be the lateral transistor of fig 1 and is connected to the first transistor 121 which can be the vertical transistor of fig 4B, see fig 12, para 89).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of SAITOH (US 20020185705).
Regarding claim 3, KOEPP discloses the semiconductor device according to claim 1.
KOEPP fails to explicitly disclose a device, wherein
the first control drift region includes a resistance reduction region and a N type base region,
the resistance reduction region has a higher N type doping concentration than the N type base region,
the resistance reduction region extends under the first control source region and the first control drain region, and
the N type base region has a portion that is disposed between the first control drain region and the resistance reduction region in the depth direction.
SAITOH teaches a device, wherein
the first control drift region (the region including 11, 32 and 10a, see fig 18, para 225) includes a resistance reduction region (fig 18, 10a, para 225) and a N type base region (fig 18, 11, para 225),
the resistance reduction region has a higher N type doping concentration than the N type base region (10a is n+ and 11 is n-, see fig 18),
the resistance reduction region extends under the first control source region and the first control drain region (10a extends under source region 13 and drain region 10b, see fig 18), and
the N type base region has a portion that is disposed between the first control drain region and the resistance reduction region in the depth direction (11 is between 10b and 10a in the vertical direction in fig 18).
KOEPP and SAITOH are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the doping region geometry of SAITOH because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the doping region geometry of SAITOH in order to improve the on resistance (See SAITOH para 127).
Regarding claim 19, KOEPP and SAITOH disclose the semiconductor device according to claim 3.
KOEPP fails to explicitly disclose a device, wherein the first control source region and the first control drain region have higher doping concentrations than the doping concentration of the resistance reduction region.
SAITOH teaches a device, wherein the first control source region and the first control drain region have higher doping concentrations than the doping concentration of the resistance reduction region (source region 13 can be doped to 1E20 per cc and 10a can be doped to 6E18 per cc, see para 117).
KOEPP and SAITOH are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the doping region geometry of SAITOH because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the doping region geometry of SAITOH in order to improve the on resistance (See SAITOH para 127).
Claim(s) 4, 13 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of NAKAGAWA (US 6118149).
Regarding claim 4, KOEPP discloses the semiconductor device according to claim 1, wherein
the control circuit unit further includes a second control element (another element in device 1 along a cross-section parallel to that in fig 2).
KOEPP fails to explicitly disclose a device comprising:
a second control source region and a second control drain region that are P type regions,
a second control gate trench section is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region.
NAKAGAWA teaches a device comprising:
a second control source region and a second control drain region that are P type regions (p-type regions 143p and 144p, see fig 64, para 144),
a second control gate trench section (fig 64, elements 146 and 147, para 136) is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region (fig 64B, 142n, para 144).
KOEPP and NAKAGAWA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the second control device of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the second control device of NAKAGAWA in order to increase the channel mobility of the device (see NAKAGAWA para 24).
Regarding claim 13, KOEPP and NAKAGAWA disclose the semiconductor device according to claim 4.
KOEPP fails to explicitly disclose a device, further comprising:
an N type inversion prevention region provided in contact with the lower end of the second control gate trench section and having a higher concentration than the second control base region,
wherein the inversion prevention region is isolated from both the second control source region and the second control drain region by the P type second control base region.
NAKAGAWA teaches a device, further comprising:
an N type inversion prevention region provided in contact with the lower end of the control gate trench section and having a higher concentration than the control base region (n+ region 151n, see fig 64B, para 152),
wherein the inversion prevention region is isolated from both the control source region and the control drain region by the P type control base region ( 142n is between both 143p and 144p and 151n, see fig 64B).
KOEPP and NAKAGAWA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the second control device of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the second control device of NAKAGAWA in order to increase the channel mobility of the device (see NAKAGAWA para 24).
Regarding claim 16, KOEPP and NAKAGAWA disclose the semiconductor device according to claim 2.
KOEPP fails to explicitly disclose a device, wherein
the control circuit unit further includes a second control element comprising:
a second control source region and a second control drain region that are P type regions,
a second control gate trench section is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region.
NAKAGAWA teaches a device, wherein
the control circuit unit further includes a second control element (the element shown in fig 63-64, see para 151-153) comprising:
a second control source region and a second control drain region that are P type regions (p-type regions 143p and 144p, see fig 64, para 144),
a second control gate trench section (fig 64, elements 146 and 147, para 136) is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region (fig 64B, 142n, para 144).
KOEPP and NAKAGAWA are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the second control device of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the second control device of NAKAGAWA in order to increase the channel mobility of the device (see NAKAGAWA para 24).
Claim(s) 5-10, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of OKAMOTO (US 20240266351).
Regarding claim 5, KOEPP discloses the semiconductor device according to claim 1.
KOEPP fails to explicitly disclose a device, wherein
the control circuit unit includes a plurality of control elements that include the first control element,
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements, wherein the isolation region is laterally surrounded by N type semiconductor on both sides.
OKAMOTO teaches a device, wherein
the control circuit unit (fig 1, ARC, para 39) includes a plurality of control elements (ARN and ARP, see fig 1, para 40) that include the first control element (the NPN transistor ARN, see fig 1, para 40),
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements (p-type region BL separates ARN and ARP, see fig 1, para 44), wherein the isolation region is laterally surrounded by N type semiconductor on both sides (at least a portion of BL is surrounded by n-type regions RDN and NW3, see fig 1, para 52).
KOEPP and OKAMOTO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 6, KOEPP discloses the semiconductor device according to claim 2.
KOEPP fails to explicitly disclose a device, wherein
the control circuit unit includes a plurality of control elements that include the first control element,
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements and separating the plurality of control elements from the power element unit, wherein the isolation region is laterally surrounded by N type semiconductor on both sides.
OKAMOTO teaches a device, wherein
the control circuit unit (fig 1, ARC, para 39) includes a plurality of control elements (ARN and ARP, see fig 1, para 40) that include the first control element (NPN element ARN, see fig 1, para 40),
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements (p-type region BL separates ARN and ARP, see fig 1, para 44) and separating the plurality of control elements from the power element unit (BL separates ARP from ARU, see fig 1), wherein the isolation region is laterally surrounded by N type semiconductor on both sides (at least a portion of BL is surrounded by n-type regions RDN and NW3, see fig 1, para 52).
KOEPP and OKAMOTO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 7, KOEPP discloses the semiconductor device according to claim 2.
KOEPP fails to explicitly disclose a device, further comprising:
a P type control high concentration region disposed to face a lower end of the first control gate trench section in a depth direction of the semiconductor substrate.
OKAMOTO teaches a device, further comprising:
a P type control high concentration region disposed to face a lower end of the first control gate trench section in a depth direction of the semiconductor substrate (p-type base layer BBL is below and faces the bottom of gates GIN and GIP, see fig 1, para 44).
KOEPP and OKAMOTO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 8, KOEPP and OKAMOTO disclose the semiconductor device according to claim 7.
KOEPP fails to explicitly disclose a device, wherein
the control high concentration region is in contact with the lower end of the first control gate trench section.
OKAMOTO teaches a device, wherein
the control high concentration region is in contact with the lower end of the first control gate trench section (BBL is in at least indirect contact with the bottom of GIN, see fig 1, para 44).
KOEPP and OKAMOTO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 9, KOEPP and OKAMOTO disclose the semiconductor device according to claim 7.
KOEPP fails to explicitly disclose a device, further comprising:
a P type power high concentration region disposed to face a lower end of the power gate trench section in the depth direction.
OKAMOTO teaches a device, further comprising:
a P type power high concentration region disposed to face a lower end of the power gate trench section in the depth direction (fig 1, TPR, para 46).
KOEPP and OKAMOTO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 10, KOEPP and OKAMOTO disclose the semiconductor device according to claim 9.
KOEPP fails to explicitly disclose a device, wherein
the control high concentration region and the power high concentration region are provided at a same position in the depth direction.
OKAMOTO teaches a device, wherein
the control high concentration region and the power high concentration region are provided at a same position in the depth direction (TPR and BBL overlap in depth, see fig 1, para 44-46).
KOEPP and OKAMOTO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 12, KOEPP and OKAMOTO disclose the semiconductor device according to claim 10.
KOEPP fails to explicitly disclose a device, wherein
the power high concentration region is disposed apart from the power gate trench section.
OKAMOTO teaches a device, wherein
the power high concentration region is disposed apart from the power gate trench section (BBL and TPR are separated by DLS, see fig 1, para 46).
KOEPP and OKAMOTO are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the multiple control circuit geometry of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of NAKAGAWA (US 6118149) and further in view of MAUDER (US 20130249602).
Regarding claim 11, KOEPP and NAKAGAWA disclose the semiconductor device according to claim 4.
KOEPP further discloses a device, further comprising:
a power element unit (device 3 that can be a vertical power transistor, see fig 1-4, para 57) that is formed in the semiconductor substrate (2 and 3 are formed in the same substrate, see fig 4) and controls whether to cause a current to flow between the upper surface and the lower surface of the semiconductor substrate (the device and the channel 35 is vertical, see fig 4, para 58), wherein
the power element unit includes: a power source region provided in the upper surface of the semiconductor substrate (fig 4B, 401, para 58);
a power drain region provided in the lower surface of the semiconductor substrate and being of a same conductivity type as the power source region (401 and 409 are the source and drain regions of a single transistor, see fig 4, 409, para 58);
a power base region provided below the power source region and being of a different conductivity type from the power source region (402 is the base region of the transistor that includes 401 and 409, see fig 4B, para 58);
a power drift region provided between the power base region and the power drain region and being of a same conductivity type as the power source region (406 is the drift region of the transistor including 401, 409 and 402, see fig 4B, para 58); and
a power gate trench section (the trench gate comprising 403, 405, 407 and 408, see fig 4B, para 58) provided from the upper surface of the semiconductor substrate to such a depth as to reach the power drift region and being in contact with the power base region (see fig 4B), and
the control circuit unit controls an operation of the power element unit (the second transistor 122 can be the lateral transistor of fig 1 and is connected to the first transistor 121 which can be the vertical transistor of fig 4B, see fig 12, para 89).
KOEPP and NAKAGAWA fail to explicitly disclose a device wherein the second control gate trench section is shorter than the power gate trench section in the depth direction and is disposed apart from the control high concentration region.
MAUDER teaches a device wherein the second control gate trench section is shorter than the power gate trench section in the depth direction and is disposed apart from the control high concentration region (the power device inside 201 can include a trench gate electrode 71 with a larger depth than that of the gate 15 or the other transistor 10, and is spaced apart from 10, see fig 21, para 67 and 113).
KOEPP, NAKAGAWA and MAUDER are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and NAKAGAWA with the trench geometry of MAUDER because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and NAKAGAWA with the trench geometry of MAUDER in order to reduce size and manufacturing costs (see MAUDER para 5).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of YAMAUCHI (US 20010030347).
Regarding claim 18, KOEPP discloses the semiconductor device according to claim 1.
KOEPP fails to explicitly disclose a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region that is provided between the first control source region and the first control drain region and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region.
YAMAUCHI teaches a device, wherein the first control element further comprises:
a P type region (high concentration region 108, see fig 16, para 95) having a higher P type doping concentration than the first control base region (fig 16, 2, para 95) that is provided between (a horizontal line can be drawn from 3 to 4 that passes through 108, see fig 16) the first control source region (fig 16, 3, para 95) and the first control drain region (fig 16, 4, para 95) and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region (108 extends from the upper surface to be level with the drift region 1c, see fig 16).
KOEPP and YAMAUCHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the high-concentration region of YAMAUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the high-concentration region of YAMAUCHI in order to reduce the internal resistance of the device (see YAMAUCHI para 95).
Claim(s) 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of SAITOH (US 20020185705) and further in view of YAMAUCHI (US 20010030347).
Regarding claim 20, KOEPP and SAITOH disclose the semiconductor device according to claim 19.
KOEPP and SAITOH fails to explicitly disclose a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region that is provided between the first control source region and the first control drain region and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region.
YAMAUCHI teaches a device, wherein the first control element further comprises:
a P type region (high concentration region 108, see fig 16, para 95) having a higher P type doping concentration than the first control base region (fig 16, 2, para 95) that is provided between (a horizontal line can be drawn from 3 to 4 that passes through 108, see fig 16) the first control source region (fig 16, 3, para 95) and the first control drain region (fig 16, 4, para 95) and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region (108 extends from the upper surface to be level with the drift region 1c, see fig 16).
KOEPP, SAITOH and YAMAUCHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the high-concentration region of YAMAUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and SAITOH with the high-concentration region of YAMAUCHI in order to reduce the internal resistance of the device (see YAMAUCHI para 95).
Regarding claim 21, KOEPP and SAITOH disclose the semiconductor device according to claim 3.
KOEPP and SAITOH fails to explicitly disclose a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region that is provided between the first control source region and the first control drain region and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region.
YAMAUCHI teaches a device, wherein the first control element further comprises:
a P type region (high concentration region 108, see fig 16, para 95) having a higher P type doping concentration than the first control base region (fig 16, 2, para 95) that is provided between (a horizontal line can be drawn from 3 to 4 that passes through 108, see fig 16) the first control source region (fig 16, 3, para 95) and the first control drain region (fig 16, 4, para 95) and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region (108 extends from the upper surface to be level with the drift region 1c, see fig 16).
KOEPP, SAITOH and YAMAUCHI are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the high-concentration region of YAMAUCHI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and SAITOH with the high-concentration region of YAMAUCHI in order to reduce the internal resistance of the device (see YAMAUCHI para 95).
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAKAGAWA (US 6118149) in view of KOEPP (US 20160268423).
Regarding claim 23, NAKAGAWA discloses a semiconductor device comprising:
a semiconductor substrate (substrate including 141, 151, 152, 142, 143 and 144, see fig 64, para 151-153) including an upper surface (upper surface of 152, see fig 64) and a lower surface (lower surface of 141, see fig 64); and
a control circuit unit formed in the semiconductor substrate and including at least one control element (the transistor shown in fig 64B, see para 152) comprising:
a control source region (fig 64, 143p, para 144) and a control drain region that are P type regions (fig 64, 144p, para 144);
a control gate trench section (fig 64, elements 146 and 147, para 136) is disposed between the control source region and the control drain region;
a control base region that is a N type region that extends from the control source region to the control drain region (fig 64B, 142n, para 144) and that includes portions that are in contact with the control gate trench section on either side of the control gate trench section below the control source region and the control drain region (see fig 64B); and
an N type inversion prevention region provided in contact with the lower end of the control gate trench section and having a higher concentration than the control base region (n+ region 151n, see fig 64B, para 152),
wherein the inversion prevention region is isolated from both the control source region and the control drain region by the P type control base region ( 142n is between both 143p and 144p and 151n, see fig 64B).
NAKAGAWA fails to explicitly disclose a device comprising a semiconductor substrate including an upper surface and a lower surface and containing silicon carbide.
KOEPP teaches a device a semiconductor substrate (the substrate 100 for circuit 2 including devices 1 and 3, see fig 1-4, para 57 and 39) including an upper surface (the upper surface of 100, see fig 1-4) and a lower surface (the lower surface of 100, see fig 1-4) and containing silicon carbide (the substrate 100 can be SiC, see para 39 and 29).
NAKAGAWA and KOEPP are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKAGAWA with the silicon carbide of KOEPP because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKAGAWA with the silicon carbide of KOEPP in order to improve the breakdown characteristics of the device (see KOEPP para 37).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-23 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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