DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7-10 and 12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 7, lines 4-7 recite “the P type first control high concentration region being provided between the resistance reduction region and a lower part of the first control drift region in the depth direction of the semiconductor substrate”. The resistance reduction region 236 and the rest of the control drift region 236 and 222 are both above the P type first control high concentration region 224 in the applicant’s disclosure. There is thus no support for the control high concentration region being between the two parts of the drift region.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 7-10 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3, lines 4-5 recite “a lower end, … a lower end”. It is not clear, from these limitations, whether the two lower ends are intended to be the same or different elements. This issue renders the claim indefinite.
Claim 7, lines 4-7 recite “the P type first control high concentration region being provided between the resistance reduction region and a lower part of the first control drift region in the depth direction of the semiconductor substrate”. The resistance reduction region is a part of the control drift region (see claim 3, from which this claim depends) and so it is not clear how the high concentration region or any else can be between them. Something cannot be between an object and itself. This issue renders the claim indefinite.
Note that dependent claims necessarily inherit any indefiniteness from the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NASU (US 20220140141).
Regarding claim 23, NASU discloses a semiconductor device comprising:
a semiconductor substrate (substrate 20 can be SiC, see fig 6-7, para 337) including an upper surface (fig 6-7, 22, para 65) and a lower surface (fig 6-7, 23, para 65) and containing silicon carbide; and
a control circuit unit (the circuit formed by the portions of the device shown in fig 6-7, see fig 5-7, para 74) formed in the semiconductor substrate and including at least one control element (the transistor element around a gate 63, see fig 6-7, para 102) comprising:
a control source region (92, see fig 6-7, para 150) and a control drain region (92, see fig 6-7, para 150) that are P type regions (although shown as n-type, the doping polarity of the device can be reversed to make them n-type, see para 336);
a control gate trench section (fig 6-7, 61, para 87) is disposed between the control source region and the control drain region (trench 61 is located between 91 and 92, see fig 6);
a control base region that is a N type region (base region 51 which is shown as p-type, but the polarity of the device can be reversed to make it n-type, see fig 6-7, para 78 and 336) that extends from the control source region to the control drain region and that includes portions that are in contact with the control gate trench section on either side of the control gate trench section below the control source region and the control drain region (51 is in contact with 61 on either side of 61 below 91 and 92, see fig 6); and
a N type inversion prevention region provided in contact with the lower end of the control gate trench section and having a higher concentration than the control base region (high concentration region 95, see fig 6-7, para 160, which can be n-type, see para 336), wherein the inversion prevention region is isolated from both the control source region and the control drain region by the control base region (51 is between 95 and 91 and also between 95 and 92, see fig 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-8 and 18-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of KAWAJI (US 6072215).
Regarding claim 1, KOEPP discloses a semiconductor device comprising:
a semiconductor substrate (the substrate 100 for circuit 2 including devices 1 and 3, see fig 1-4, para 57 and 39) including an upper surface (the upper surface of 100, see fig 1-4) and a lower surface (the lower surface of 100, see fig 1-4) and containing silicon carbide (the substrate 100 can be SiC, see para 39 and 29); and
a control circuit unit (the device 1 formed in 2, see fig 1-4, para 35) formed in the semiconductor substrate and including at least a first control element (the element of 1 whose cross-section is shown in fig 2, see para 39).
KOEPP fails to explicitly disclose a device wherein a semiconductor substrate including an upper surface and a lower surface; and
a control circuit unit formed in the semiconductor substrate and including at least a first control element comprising:
a first control source region provided in the upper surface of the semiconductor substrate;
a first control drain region provided in the upper surface of the semiconductor substrate and being of a same conductivity type as the first control source region;
a first control base region provided in contact with the first control source region and being of a different conductivity type from the first control source region; and
a first control gate trench section provided from the upper surface of the semiconductor substrate to an internal portion of the semiconductor substrate and being in contact with the first control base region,
the first control source region being provided between the first control gate trench section and the first control drain region such that the first control drain region is spaced apart from the first control gate trench section,
wherein the first control source region and the first control drain region are N type regions,
the first control base region is a P type region provided below the first control source region,
a N type first control drift region connects the first control base region to the first control drain region,
the first control gate trench section is in contact with the first control base region, from a boundary between the first control source region and the first control base region to a boundary between the first control drift region and the first control base region,
the first control drift region extends under the first control source region and the first control drain region, and
the first control base region is disposed between the first control source region and the first control drift region in a depth direction of the semiconductor substrate.
KAWAJI teaches a device wherein a semiconductor substrate (the substrate including 10 and 14, see fig 1, para 11) including an upper surface (the upper surface of 14, see fig 1) and a lower surface (the lower surface of 10, see fig 1); and
a control circuit unit formed in the semiconductor substrate (the substrate including 10 and 14, see fig 1, para 11) and including at least a first control element (the circuit 100 including the device shown in fig 1) comprising:
a first control source region (fig 1, 18, para 12) provided in the upper surface of the semiconductor substrate (18 is on the upper surface of 14, see fig 1);
a first control drain region (a portion of drain region 20 directly under drain contact 46, see fig 1, para 12) provided in the upper surface of the semiconductor substrate (20 is on an upper surface of 14, see fig 1) and being of a same conductivity type as the first control source region (18 and 20 are n-type, see fig 1);
a first control base region (fig 1, 16, para 12) provided in contact with the first control source region (18 is in contact with 16, see fig 1) and being of a different conductivity type from the first control source region (16 is p-type, see fig 1, para 12); and
a first control gate trench section (the trench 74 and its contents, see fig 1, para 13) provided from the upper surface of the semiconductor substrate to an internal portion of the semiconductor substrate and being in contact with the first control base region (74 goes from the top of 14 to an interior of 10, and is in contact with 16, see fig 1),
the first control source region being provided between the first control gate trench section and the first control drain region such that the first control drain region is spaced apart from the first control gate trench section (18 is between 20 and 74, and 20 is spaced apart from 74, see fig 1),
wherein the first control source region and the first control drain region are N type regions (18 and 20 are n-type, see fig 1),
the first control base region is a P type region provided below the first control source region (16 is below 18 and is p-type, see fig 1),
a N type first control drift region connects the first control base region to the first control drain region (the n-type region comprising n- region 15 and the lower part of 20 level with 15 connects 16 to the upper drain region of 20, see fig 1, para 14),
the first control gate trench section is in contact with the first control base region, from a boundary between the first control source region and the first control base region to a boundary between the first control drift region and the first control base region (74 is in direct contact with 16 from the border of 16 and 18 to the border of 16 and 15, see fig 1),
the first control drift region extends under the first control source region and the first control drain region (15 extends under 16 and the upper portion of 20, see fig 1), and
the first control base region is disposed between the first control source region and the first control drift region in a depth direction of the semiconductor substrate (16 is between 18 and 15 in the vertical direction, see fig 1).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 2, KOEPP and KAWAKJI disclose the semiconductor device according to claim 1.
KOEPP further discloses a device, further comprising:
a power element unit (device 3 that can be a vertical power transistor, see fig 1-4, para 57) that is formed in the semiconductor substrate (2 and 3 are formed in the same substrate, see fig 4) and controls whether to cause a current to flow between the upper surface and the lower surface of the semiconductor substrate (the device and the channel 35 is vertical, see fig 4, para 58),
wherein
the power element unit includes: a power source region provided in the upper surface of the semiconductor substrate (fig 4B, 401, para 58);
a power drain region provided in the lower surface of the semiconductor substrate and being of a same conductivity type as the power source region (401 and 409 are the source and drain regions of a single transistor, see fig 4, 409, para 58);
a power base region provided below the power source region and being of a different conductivity type from the power source region (402 is the base region of the transistor that includes 401 and 409, see fig 4B, para 58);
a power drift region provided between the power base region and the power drain region and being of a same conductivity type as the power source region (406 is the drift region of the transistor including 401, 409 and 402, see fig 4B, para 58); and
a power gate trench section (the trench gate comprising 403, 405, 407 and 408, see fig 4B, para 58) provided from the upper surface of the semiconductor substrate to such a depth as to reach the power drift region and being in contact with the power base region (see fig 4B), and
the control circuit unit controls an operation of the power element unit (the second transistor 122 can be the lateral transistor of fig 1 and is connected to the first transistor 121 which can be the vertical transistor of fig 4B, see fig 12, para 89).
Regarding claim 3, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 1.
KOEPP further discloses a device, wherein the resistance reduction region has a higher N type doping concentration than the N type base region (205 has a higher doping concentration than 260, see fig 2, para 35).
KOEPP fails to explicitly disclose a device, wherein the first control drift region includes a resistance reduction region and a N type base region,
the N type base region has a lower end,
the first control base region has a lower end,
the resistance reduction region extends under the first control source region and the first control drain region,
the resistance reduction region is in contact with both the first control gate trench section and the lower end of the first control base region such that there is a boundary between the resistance reduction region and the first control base region and
and the first control gate trench section is in contact with the first control base region from the boundary between the first control source region and the first control base region to the boundary between the resistance reduction region and the first control base region, and
the N type base region has a portion that is disposed between the first control drain region and the resistance reduction region in the depth direction such that the resistance reduction region is in contact with the lower end of the N type base region under the first control drain region.
KAWAJI teaches a device, wherein the first control drift region includes a resistance reduction region (the n- region 15, see fi g1, para 4) and a N type base region (the lower region of 20 level with 15, see fig 1, para 4),
the N type base region has a lower end (the lower end of 20 bordering 10, see fig 1),
the first control base region has a lower end (16 has a bottom surface bordering 15, see fig 1),
the resistance reduction region extends under the first control source region and the first control drain region (15 extends under 18 and the upper part of 20, see fig 1),
the resistance reduction region is in contact with both the first control gate trench section and the lower end of the first control base region (15 is in contact with 72 and with the lower part of 20, see fig 1) such that there is a boundary between the resistance reduction region and the first control base region (there is a border between 15 and 16, see fig 1) and
the first control gate trench section is in contact with the first control base region from the boundary between the first control source region and the first control base region to the boundary between the resistance reduction region and the first control base region (16 is in contact with 72 from 18 to 15, see fig 1), and
the N type base region has a portion that is disposed between the first control drain region and the resistance reduction region in the depth direction (the lower part of 20 is between the upper part of 20 and 15, see fig 1) such that the resistance reduction region is in contact with the lower end of the N type base region under the first control drain region (15 is in contact with the lower part of 20 under the upper part of 20, see fig 1).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 7, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 3.
KOEPP fails to explicitly disclose a device, further comprising:
a P type first control high concentration region disposed to face a lower end of the first control gate trench section in the depth direction of the semiconductor substrate,
the P type first control high concentration region being provided between the resistance reduction region and a lower part of the first control drift region in the depth direction of the semiconductor substrate.
KAWAJI teaches a device, further comprising:
a P type first control high concentration region (p-region 10, see fig 1, para 4) disposed to face a lower end of the first control gate trench section in the depth direction of the semiconductor substrate (10 faces a bottom of 74, see fig 1),
the P type first control high concentration region being provided between the resistance reduction region and a lower part of the first control drift region in the depth direction of the semiconductor substrate (10 is below 15, see fig 1).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 8, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 7.
KOEPP fails to explicitly disclose a device, wherein
the P type first control high concentration region is in contact with the lower end of the first control gate trench section.
KAWAJI teaches a device, wherein
the P type first control high concentration region is in contact with the lower end of the first control gate trench section (10 is in contact with the lower end of 74, see fig 1).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 18, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 1.
KOEPP fails to explicitly disclose a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region that is provided between the first control source region and the first control drain region and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region.
KAWAJI teaches a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region (17 is a p+ region, and 16 is n-, see fig 1, para 4) that is provided between the first control source region and the first control drain region (17 is between 18 and 20, see fig 1) and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region (17 extends from the top surface to 16, see fig 1).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 19, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 3.
KOEPP fails to explicitly disclose a device, wherein the first control source region and the first control drain region have higher doping concentrations than the doping concentration of the resistance reduction region.
KAWAJI teaches a device, wherein the first control source region and the first control drain region have higher doping concentrations than the doping concentration of the resistance reduction region (18 and 20 are n+ and 15 is n-type, see fig 1, para 5).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 20, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 19.
KOEPP fails to explicitly disclose a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region that is provided between the first control source region and the first control drain region and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region.
KAWAJI teaches a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region (17 is a p+ region, and 16 is n-, see fig 1, para 4) that is provided between the first control source region and the first control drain region (17 is between 18 and 20, see fig 1) and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region (17 extends from the top surface to 16, see fig 1).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 21, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 3.
KOEPP fails to explicitly disclose a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region that is provided between the first control source region and the first control drain region and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region.
KAWAJI teaches a device, wherein the first control element further comprises:
a P type region having a higher P type doping concentration than the first control base region (17 is a p+ region, and 16 is n-, see fig 1, para 4) that is provided between the first control source region and the first control drain region (17 is between 18 and 20, see fig 1) and extends in the depth direction from the upper surface of the semiconductor substrate to the first control drift region (17 extends from the top surface to 16, see fig 1).
KOEPP and KAWAJI are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the additional device geometry of KAWAJI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the additional device geometry of KAWAJI in order to decrease the on-resistance (see KAWAJI para 21).
Regarding claim 22, KOEPP and KAWAKJI disclose the semiconductor device according to claim 1.
KOEPP further discloses a device, further comprising:
a power element unit (device 3 that can be a vertical power transistor, see fig 1-4, para 57) that is formed in the semiconductor substrate (2 and 3 are formed in the same substrate, see fig 4) and controls whether to cause a current to flow between the upper surface and the lower surface of the semiconductor substrate (the device and the channel 35 is vertical, see fig 4, para 58), wherein
the power element unit includes: a power source region provided in the upper surface of the semiconductor substrate (fig 4B, 401, para 58);
a power drain region provided in the lower surface of the semiconductor substrate and being of a same conductivity type as the power source region (401 and 409 are the source and drain regions of a single transistor, see fig 4, 409, para 58);
a power base region provided below the power source region and being of a different conductivity type from the power source region (402 is the base region of the transistor that includes 401 and 409, see fig 4B, para 58);
a power drift region provided between the power base region and the power drain region and being of a same conductivity type as the power source region (406 is the drift region of the transistor including 401, 409 and 402, see fig 4B, para 58); and
a pair of power gate trench sections (a pair of the trench gate comprising 403, 405, 407 and 408, see fig 4B, para 58) provided from the upper surface of the semiconductor substrate to such a depth as to reach the power drift region and being in contact with the power base region (see fig 4B),
wherein the power base region and the power source region are disposed between the pair of power gate trench sections (401 and 402 are between trenches 408, see fig 4B),
the control circuit unit controls an operation of the power element unit (the second transistor 122 can be the lateral transistor of fig 1 and is connected to the first transistor 121 which can be the vertical transistor of fig 4B, see fig 12, para 89).
Claim(s) 4, 13 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of KAWAJI (US 6072215) and further in view of NAKAGAWA (US 6118149).
Regarding claim 4, KOEPP and KAWAKJI disclose the semiconductor device according to claim 1.
KOEPP further discloses a device, wherein
the control circuit unit further includes a second control element (another element in device 1 along a cross-section parallel to that in fig 2).
KOEPP fails to explicitly disclose a device comprising:
a second control source region and a second control drain region that are P type regions,
a second control gate trench section is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region.
NAKAGAWA teaches a device comprising:
a second control source region and a second control drain region that are P type regions (p-type regions 143p and 144p, see fig 64, para 144),
a second control gate trench section (fig 64, elements 146 and 147, para 136) is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region (fig 64B, 142n, para 144).
KOEPP, KAWAJI and NAKAGAWA are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the second device of opposite doping polarity of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the second device of opposite doping polarity of NAKAGAWA in order to increase the channel mobility of the device (see NAKAGAWA para 24).
Regarding claim 13, KOEPP and KAWAKJI disclose the semiconductor device according to claim 4.
KOEPP fails to explicitly disclose a device, further comprising:
a N type inversion prevention region provided in contact with the lower end of the second control gate trench section and having a higher concentration than the second control base region,
wherein the inversion prevention region is isolated spaced apart from both the second control source region and the second control drain region by the N type second control base region being present between the inversion prevention region and both the second control source region and the second control drain region.
NAKAGAWA teaches a device, further comprising:
a N type inversion prevention region provided in contact with the lower end of the second control gate trench section (151n is at least indirectly in contact with 146, see fig 64B, para 152) and having a higher concentration than the second control base region (151 is n+ and 142 is n type, see fig 64B, para 152),
wherein the inversion prevention region is isolated spaced apart from both the second control source region and the second control drain region by the N type second control base region being present between the inversion prevention region and both the second control source region and the second control drain region (151n is separated from 143p and 144p by 142n, see fig 64B).
KOEPP, KAWAJI and NAKAGAWA are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the second device of opposite doping polarity of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the second device of opposite doping polarity of NAKAGAWA in order to increase the channel mobility of the device (see NAKAGAWA para 24).
Regarding claim 16, KOEPP and KAWAKJI disclose the semiconductor device according to claim 2.
KOEPP fails to explicitly disclose a device, wherein
the control circuit unit further includes a second control element comprising:
a second control source region and a second control drain region that are P type regions,
a second control gate trench section is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region.
NAKAGAWA teaches a device, wherein
the control circuit unit further includes a second control element (the element shown in fig 63-64, see para 151-153) comprising:
a second control source region and a second control drain region that are P type regions (p-type regions 143p and 144p, see fig 64, para 144),
a second control gate trench section (fig 64, elements 146 and 147, para 136) is disposed between the second control source region and the second control drain region, and
a second control base region that is a N type region that extends from the second control source region to the second control drain region and that includes portions that are in contact with the second control gate trench section on either side of the second control gate trench section below the second control source region and the second control drain region (fig 64B, 142n, para 144).
KOEPP, KAWAJI and NAKAGAWA are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the second device of opposite doping polarity of NAKAGAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the second device of opposite doping polarity of NAKAGAWA in order to increase the channel mobility of the device (see NAKAGAWA para 24).
Claim(s) 5-6, 9-10 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of KAWAJI (US 6072215) and further in view of OKAMOTO (US 20240266351).
Regarding claim 5, KOEPP and KAWAKJI disclose the semiconductor device according to claim 1.
KOEPP fails to explicitly disclose a device, wherein
the control circuit unit includes a plurality of control elements that include the first control element,
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements, wherein the isolation region is laterally surrounded by N type semiconductor on both sides.
OKAMOTO teaches a device, wherein
the control circuit unit (fig 1, ARC, para 39) includes a plurality of control elements (ARN and ARP, see fig 1, para 40) that include the first control element (the NPN transistor ARN, see fig 1, para 40),
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements (p-type region BL separates ARN and ARP, see fig 1, para 44), wherein the isolation region is laterally surrounded by N type semiconductor on both sides (at least a portion of BL is surrounded by n-type regions RDN and NW3, see fig 1, para 52).
KOEPP, KAWAJI and OKAMOTO are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 6, KOEPP and KAWAKJI disclose the semiconductor device according to claim 2.
KOEPP fails to explicitly disclose a device, wherein
the control circuit unit includes a plurality of control elements that include the first control element,
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements and separating the plurality of control elements from the power element unit, wherein the isolation region is laterally surrounded by N type semiconductor on both sides.
OKAMOTO teaches a device, wherein
the control circuit unit (fig 1, ARC, para 39) includes a plurality of control elements (ARN and ARP, see fig 1, para 40) that include the first control element (NPN element ARN, see fig 1, para 40),
the semiconductor device further comprising:
a P type isolation region separating each of the plurality of control elements from a neighboring one of the plurality of control elements (p-type region BL separates ARN and ARP, see fig 1, para 44) and separating the plurality of control elements from the power element unit (BL separates ARP from ARU, see fig 1), wherein the isolation region is laterally surrounded by N type semiconductor on both sides (at least a portion of BL is surrounded by n-type regions RDN and NW3, see fig 1, para 52).
KOEPP, KAWAJI and OKAMOTO are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 9, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 7.
KOEPP fails to explicitly disclose a device, further comprising:
a P type power high concentration region disposed to face a lower end of the power gate trench section in the depth direction.
OKAMOTO teaches a device, further comprising:
a P type power high concentration region disposed to face a lower end of the power gate trench section in the depth direction (fig 1, TPR, para 46).
KOEPP, KAWAJI and OKAMOTO are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 10, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 9.
KOEPP fails to explicitly disclose a device, wherein
the control high concentration region and the power high concentration region are provided at a same position in the depth direction.
OKAMOTO teaches a device, wherein
the control high concentration region and the power high concentration region are provided at a same position in the depth direction (TPR and BBL overlap in depth, see fig 1, para 44-46).
KOEPP, KAWAJI and OKAMOTO are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Regarding claim 12, as best as the examiner is able to ascertain the claimed invention, KOEPP and KAWAKJI disclose the semiconductor device according to claim 10.
KOEPP fails to explicitly disclose a device, wherein
the power high concentration region is disposed apart from the power gate trench section.
OKAMOTO teaches a device, wherein
the power high concentration region is disposed apart from the power gate trench section (BBL and TPR are separated by DLS, see fig 1, para 46).
KOEPP, KAWAJI and OKAMOTO are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP and KAWAJI with the additional control element of OKAMOTO in order to improve the breakdown voltage (see OKAMOTO para 49).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over KOEPP (US 20160268423) in view of KAWAJI (US 6072215) and NAKAGAWA (US 6118149) and further in view of MAUDER (US 20130249602).
Regarding claim 11, KOEPP, KAWAKJI and NAKAGAWA disclose the semiconductor device according to claim 4.
KOEPP further discloses a device, further comprising:
a power element unit (device 3 that can be a vertical power transistor, see fig 1-4, para 57) that is formed in the semiconductor substrate (2 and 3 are formed in the same substrate, see fig 4) and controls whether to cause a current to flow between the upper surface and the lower surface of the semiconductor substrate (the device and the channel 35 is vertical, see fig 4, para 58), wherein
the power element unit includes: a power source region provided in the upper surface of the semiconductor substrate (fig 4B, 401, para 58);
a power drain region provided in the lower surface of the semiconductor substrate and being of a same conductivity type as the power source region (401 and 409 are the source and drain regions of a single transistor, see fig 4, 409, para 58);
a power base region provided below the power source region and being of a different conductivity type from the power source region (402 is the base region of the transistor that includes 401 and 409, see fig 4B, para 58);
a power drift region provided between the power base region and the power drain region and being of a same conductivity type as the power source region (406 is the drift region of the transistor including 401, 409 and 402, see fig 4B, para 58); and
a power gate trench section (the trench gate comprising 403, 405, 407 and 408, see fig 4B, para 58) provided from the upper surface of the semiconductor substrate to such a depth as to reach the power drift region and being in contact with the power base region (see fig 4B), and
the control circuit unit controls an operation of the power element unit (the second transistor 122 can be the lateral transistor of fig 1 and is connected to the first transistor 121 which can be the vertical transistor of fig 4B, see fig 12, para 89).
KOEPP, KAWAKJI and NAKAGAWA fails to explicitly disclose a device wherein the second control gate trench section has a lower end, the second control element further includes a control high concentration region disposed to face the lower end of the second control gate trench section in the depth direction of the semiconductor substrate, and
the second control gate trench section is shorter than the power gate trench section in the depth direction and is disposed apart from the control high concentration region.
MAUDER teaches a device wherein the second control gate trench section has a lower end (the second gate trench 15 has a lower end, see fig 21), the second control element further includes a control high concentration region disposed to face the lower end of the second control gate trench section in the depth direction of the semiconductor substrate (11 faces the bottom of 15 in the depth direction, see fig 21, para 35), and
the second control gate trench section is shorter than the power gate trench section in the depth direction and is disposed apart from the control high concentration region (the power device inside 201 can include a trench gate electrode 71 with a larger depth than that of the gate 15 or the other transistor 10, and is spaced apart from 11, see fig 21, para 67 and 113).
KOEPP and MAUDER are analogous art because they both are directed towards semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KOEPP with the second control device configuration of MAUDER because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KOEPP with the second control device configuration of MAUDER in order to reduce size and manufacturing costs (see MAUDER para 5).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 23 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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