DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 30, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 22 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 22: Such subject matter of “the plurality of memory cells associated with the identified page remain in the first state after the output is generated” is not disclosed in the original disclosure; hence, this subject matter is deemed new matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-6, 10, 12-13, 15, 19 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 2020/0036539 A1; “Hung”) in view of Ju et al. (US 2022/0050608 A1; “Ju”).
Regarding claim 1: Hung (a device in FIG. 1, FIG. 2, and FIG. 3 using method of FIG. 4A-B, 4E, FIG. 6, [0069-0080, 0089-0091]) teaches a method for generating a random number using a non-volatile memory based physical unclonable function (PUF), comprising:
identifying a page of a memory die of a non-volatile memory device (“A device as described, for example, which is implemented in a single packaged integrated circuit or multichip module that comprises a non-volatile memory array including a plurality of blocks of memory cells with a security key stored in a particular block” is stated in [0016]; starting distribution 500 is established by using a page erase operation as stated in [0072]; hence, a page is identified);
causing each of a plurality of memory cells associated with the identified page to be in a first state (an erased state represented by starting distribution 500 in FIG. 4A);
determining an initial read threshold voltage (a threshold voltage corresponding to the dividing line in FIG. 4B is determined such as by using the steps in FIG. 6);
performing a soft read operation on the plurality of memory cells using the initial read threshold voltage, wherein the soft read operation using the initial read threshold voltage causes a subset of memory cells of the plurality of memory cells that are in the first state to be read as being in a second state, wherein the second state is different from the first state (as seen in FIG. 4B or 4E, for example, wherein cells in the initial distribution state that have a threshold voltage below the dividing line are read as being in a data “1” state and cells in the initial distribution state that have a threshold voltage above the dividing line are read as being a data “0”);
determining whether a number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to a number of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6; see “it may be desirable that the ratio of zeros to ones be close to 1” in [0076]);
generating an output ([0017-0022]; an output data set that is a PUF-based data set; see step 260 in FIG. 6) based, at least in part, on determining that the number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to the number of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6; using a ratio of 1 in these steps as disclosed in [0076]), wherein the output is a random number (“random key” in [0011]; “random keys” in [0015], see “sufficient randomness” in [0171], [0175], [0182]) represented by respective states read from a plurality of memory cells associated with the identified page using a read threshold voltage (the dividing line) at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state; and
providing the output to a computing device (see “A PUF then provides or is used to provide a unique data set, which unique data set is accessible on a bus 131 by the security logic 125 through a PUF program controller 140 on bus 141, and utilized by the security logic in communications across line 122 with the access control block 115” in [0054-0057]; the data on either bus 141 or on bus 131 may be considered to be the output, and either one of 140 and 125 in FIG. 1 or both may be referred to as a computing device; also see output from 440 to processor system 410 in FIG. 2).
Hung does not specifically teach the output random number is represented by respective states read from each of the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state.
Ju ([0041, 0047, 0073, 0075, 0086, 0130]) teaches storing or programming a security key to a single page of a memory, and also teaches a writing or a reading operation of the memory is performed on a page basis.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Ju into the device and/or method of Hung in a manner such that all of the memory cells in the distribution of 500, which Hung ([0072] of Hung) already discloses as being a result of a page erase operation, would be a of a single page used to store the security key such that each of the plurality of memory cells of the page would be read when reading the security key. Hence, the output random number would be represented by respective states read from each of the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state. The motivation to do so would have been to use a single page to store the security key, which was already known to be suitable as exemplified by Ju, and to read the security key by reading all of the memory cells of the page in which the security key is stored, wherein a read operation is well known in the art to be performed in a unit of a page as also exemplified by Ju.
Regarding claim 3: Hung teaches the method of claim 1, further comprising determining a second read threshold voltage based on determining that the number of memory cells that are in the first state and are read as being in the second state is substantially higher or substantially lower than the number of memory cells that are in the first state and are read as being in the first state (see 240 in FIG. 6 or 1340 in FIG. 13).
Regarding claim 4: Hung teaches the method of claim 3, further comprising:
performing a subsequent soft read operation on the plurality of memory cells using the second read threshold voltage, wherein the subsequent soft read operation using the second read threshold voltage causes a second subset of memory cells of the plurality of memory cells that are in the first state to be read as being in a second state that is different from the first state (performing 210 at a time after performing 240 in FIG. 6 or performing 1310 after performing 1340 in FIG. 13); and
determining whether a number of memory cells in the second subset of memory cells that are in the first state and are read as being in the second state is substantially equivalent to a number of memory cells in the second subset of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6 after another iteration of 210 or step 1330 in FIG. 13 after another iteration of 1310).
Regarding claim 5: Hung teaches the method of claim 4, further comprising:
generating the output based, at least in part, on determining that the number of memory cells in the second subset of memory cells that are in the first state and are read as being in the second state is substantially equivalent to the number of memory cells in the second subset of memory cells that are in the first state and are read as being in the first state (260 in FIG. 6 or 1370 in FIG. 13; using a ratio of 1 as disclosed in [0076]); and
providing the output to the computing device (see “A PUF then provides or is used to provide a unique data set, which unique data set is accessible on a bus 131 by the security logic 125 through a PUF program controller 140 on bus 141, and utilized by the security logic in communications across line 122 with the access control block 115” in [0054-0057]; the data on either bus 141 or on bus 131 may be considered to be the output, and either one of 140 and 125 in FIG. 1 or both may be referred to as a computing device; also see output from 440 to processor system 410 in FIG. 2).
Regarding claim 6: Hung teaches the method of claim 1, wherein identifying the page of the memory die comprises identifying an address of the identified page (since “a page erase operation” in [0072] inherently requires identifying a page to erase by an address then Hung’s invention inherently identifies an address of the page in order to perform the page erase operation).
Regarding claim 10: Hung teaches the first state is a state in which the plurality of memory cells are in an erased state (see “a page erase operation” in [0072]).
Regarding claim 12: Hung (a device in FIG. 1, FIG. 2, and FIG. 3 using method of FIG. 4A-B, 4E, FIG. 6, [0069-0080, 0089-0091]) teaches a data storage device, comprising:
at least one memory die (see “multichip module” in 0016] or “system-on-a-chip SOC” in [0053-0054]); and
a controller (125 and 140 in FIG. 1, [0054-0057] or processor system 410 in FIG. 2, [0061]) communicatively coupled to the at least one memory die and configured to:
identify a page of the at least one memory die (“A device as described, for example, which is implemented in a single packaged integrated circuit or multichip module that comprises a non-volatile memory array including a plurality of blocks of memory cells with a security key stored in a particular block” is stated in [0016]; starting distribution 500 is established by using a page erase operation as stated in [0072]; hence, a page is identified);
cause each of a plurality of memory cells associated with the identified page to be in a first state (starting distribution 500 in FIG. 4A or 1200 in FIG. 12A);
determine an initial read threshold voltage (a threshold voltage corresponding to the dividing line in FIG. 4B or read voltage VR in FIG. 12B);
perform a soft read operation on the plurality of memory cells using the initial read threshold voltage, wherein the soft read operation using the initial read threshold voltage causes a subset of memory cells of the plurality of memory cells that are in the first state to be read as being in a second state that is different from the first state (as seen in FIG. 4B or FIG. 12B, for example, wherein cells in the initial distribution state that have a threshold voltage below the dividing line are read as being in a data “1” state and cells in the initial distribution state that have a threshold voltage above the dividing line are read as being a data “0”);
determine whether a number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to a number of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6 or 1330 in FIG. 13 using a ratio of 1; see “it may be desirable that the ratio of zeros to ones be close to 1” in [0076]); and
generating an output ([0017-0022]; an output data set that is a PUF-based data set; see step 260 in FIG. 6) based, at least in part, on determining that the number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to the number of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6; using a ratio of 1 in these steps as disclosed in [0076]), wherein the output is a random number (“random key” in [0011]; “random keys” in [0015], see “sufficient randomness” in [0171], [0175], [0182]) represented by respective states read from a plurality of memory cells associated with the identified page using a read threshold voltage (the dividing line) at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state.
Hung does not specifically teach the output random number is represented by respective states read from each of the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state.
Ju ([0041, 0047, 0073, 0075, 0086, 0130]) teaches storing or programming a security key to a single page of a memory, and also teaches a writing or a reading operation of the memory is performed on a page basis.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Ju into the device and/or method of Hung in a manner such that all of the memory cells in the distribution of 500, which Hung ([0072] of Hung) already discloses as being a result of a page erase operation, would be a of a single page used to store the security key such that each of the plurality of memory cells of the page would be read when reading the security key. Hence, the output random number would be represented by respective states read from each of the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state. The motivation to do so would have been to use a single page to store the security key, which was already known to be suitable as exemplified by Ju, and to read the security key by reading all of the memory cells of the page in which the security key is stored, wherein a read operation is well known in the art to be performed in a unit of a page as also exemplified by Ju.
Regarding claim 13: Hung teaches the controller is further configured to provide the output to a computing device (either one of 140 and 125 in FIG. 1 or both may be referred to as a computing device; Also, see “The output data set can be provided to an external system, such as the system controlling execution of the PUF for use as a shared secret in a security protocol” in [0091] and “The output data set can be provided to an external system, such as the system controlling execution of the PUF for use as a shared secret in a security protocol.“ in [0126]).
Regarding claim 15: Hung teaches claim 12, wherein identifying the page of the memory die comprises identifying an address of the identified page (since “a page erase operation” in [0072] inherently requires identifying a page to erase by an address then Hung’s invention inherently identifies an address of the page in order to perform the page erase operation).
Regarding claim 22: Hung teaches the data storage device of claim 12, wherein the plurality of memory cells associated with the identified page remain in the first state during the soft read operation and after the output is generated (for types of memory cells, wherein there is no substantial threshold voltage drift over time, the distribution 500 remains; it is important to note that FIG. 4C is an additional technique that does not limit or preclude the use of FIG. 4B as being a stable data set for a long enough time to output the read security key; Hung in [0077-0080] makes it clear that there CAN be or MAY be threshold voltage drift over time “for some types of memory cells” and FIG. 4C is an example of an additional technique that can be used to generate an improved read margin to compensate for such drift IF such memory cells are used BUT it is understood that NOT ALL memory cells have such a threshold voltage drift).
Regarding claim 19: Hung (a device in FIG. 1, FIG. 2, and FIG. 3 using method of FIG. 4A-B, 4E, FIG. 6, [0069-0080, 0089-0091]) teaches a non-volatile storage device, comprising:
a plurality of storage means (memory cells in a “multichip module” in [0016] or “system-on-a-chip SOC” in [0052-0060]);
processing means (either one of 140 and 125 in FIG. 1 or both) operable to:
cause a plurality of memory means (PUF memory cells in Flash Memory Array 130) associated with at least one of the plurality of memory storage means to be in a first state (starting distribution 500 in FIG. 4A);
perform a soft read operation on the plurality of memory means (cells) using an initial read threshold voltage, wherein the soft read operation using the initial read threshold voltage causes a subset of memory means of the plurality of memory means that are in the first state to be read as being in a second state that is different from the first state (as seen in FIG. 4B, for example, wherein cells in the initial distribution state that have a threshold voltage below the dividing line are read as being in a data “1” state and cells in the initial distribution state that have a threshold voltage above the dividing line are read as being a data “0”);
determine whether a number of memory means that are in the first state and are read as being in the second state is substantially equivalent to a number of memory means that are in the first state and are read as being in the first state (step 230 in FIG. 6; see “it may be desirable that the ratio of zeros to ones be close to 1” in [0076]); and
generate an output ([0017-0022]; an output data set that is a PUF-based data set; see step 260 in FIG. 6) based, at least in part, on a determination that the number of memory means that are in the first state and are read as being in the second state is substantially equivalent to the number of memory means that are in the first state and are read as being in the first state (step 230 in FIG. 6; using a ratio of 1 in these steps as disclosed in [0076]).
Hung does not specifically teach the output random number is represented by respective states read from each of the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state.
Ju ([0041, 0047, 0073, 0075, 0086, 0130]) teaches storing or programming a security key to a single page of a memory, and also teaches a writing or a reading operation of the memory is performed on a page basis.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Ju into the device and/or method of Hung in a manner such that all of the memory cells in the distribution of 500, which Hung ([0072] of Hung) already discloses as being a result of a page erase operation, would be a of a single page used to store the security key such that each of the plurality of memory cells of the page would be read when reading the security key. Hence, the output random number would be represented by respective states read from each of the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state. The motivation to do so would have been to use a single page to store the security key, which was already known to be suitable as exemplified by Ju, and to read the security key by reading all of the memory cells of the page in which the security key is stored, wherein a read operation is well known in the art to be performed in a unit of a page as also exemplified by Ju.
Claim(s) 7, 16, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 2020/0036539 A1) as modified by Ju (US 2022/0050608 A1) and further in view of Fujita et al. (US 2021/0303182 A1).
Regarding claims 7 and 21: Hung as modified above ([0072] of Hung) already teaches causing the plurality of memory cells associated with the identified page to be caused to be in the first state; however, Hung does not specifically teach:
storing the address of the identified page in the non-volatile memory device;
retrieving the address of the identified page from the non-volatile memory device; and
reproducing the output by performing a subsequent read operation on the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state.
Fujita ([0032-0033]; FIG. 5A) teaches generating a random sequence as part of implementing a NAND PUF in a manner similar to that taught by Hung, wherein a page of memory cells in a memory array having a threshold voltage distribution is divided by a using a read threshold voltage approximately in the middle of the distribution, and the page address of the stored random sequence may be stored on the NAND flash memory chip itself., for example, in another page of the NAND flash memory chip. Furthermore, Fujita teaches the natural random sequence may be retrieved and read using the page address that is stored.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fujita into Hung in a manner such that:
the address of the identified page would be stored in the non-volatile memory device;
the address of the identified page would be retrieved from the non-volatile memory device; and
the output would be reproduced by performing a subsequent read operation on the plurality of memory cells associated with the identified page using the read threshold voltage at which the number of memory cells read as being in the second state is substantially equivalent to the number of memory cells read as being in the first state
The motivation to do so would have been to store the page address of the random number so that the random number may be read to determine key needed to enable access to data, or to decrypt or encrypt data, stored in the blocks in the plurality of blocks (see [0016] of Hung).
Regarding claim 16: Hung does not specifically teach the controller is further configured to cause the address of the identified page to be stored in the data storage device.
Fujita ([0032-0033]; FIG. 5A) teaches generating a random sequence as part of implementing a NAND PUF in a manner similar to that taught by Hung, wherein a page of memory cells in a memory array having a threshold voltage distribution is divided by a using a read threshold voltage approximately in the middle of the distribution, and the address of the stored random sequence may be stored on the NAND flash memory chip itself., for example, in another page of the NAND flash memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fujita into Hung in a manner such that the controller would be further configured to cause the address of the identified page to be stored in the data storage device like that taught by Fujita. The motivation to do so would have been to store the page address of the random number so that the random number may be read to determine key needed to enable access to data, or to decrypt or encrypt data, stored in the blocks in the plurality of blocks (see [0016] of Hung).
Regarding claim 20: Hung does not specifically teach the non-volatile storage device of claim 19, wherein the processing means is further operable to store an address[,] associated with the at least one of the plurality of memory storage means[,] in the non-volatile storage device.
Fujita ([0032-0033]; FIG. 5A) teaches generating a random sequence as part of implementing a NAND PUF in a manner similar to that taught by Hung, wherein a page of memory cells in a memory array having a threshold voltage distribution is divided by a using a read threshold voltage approximately in the middle of the distribution, and the address of the stored random sequence may be stored on the NAND flash memory chip itself, for example, in another page of the NAND flash memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fujita into Hung in a manner such that the address of the identified page would be stored in the non-volatile memory device like that taught by Fujita by the controller, such as stored into another page of the memory array. The motivation to do so would have been to store the page address of the random number so that the random number may be read to determine the key needed to enable access to data, or to decrypt or encrypt data, stored in the blocks in the plurality of blocks (see [0016] of Hung).
Claim(s) 8-9 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 2020/0036539 A1) as modified by Ju (US 2022/0050608 A1), and further in view of Asnaashari (US 20230317158 A1).
Regarding claims 8-9: Hung does not specifically teach generating parity bits in the non-volatile memory device, (regarding claim 9) and storing the parity bits in the non-volatile memory device.
Asnaashari ([0051]) teaches “Upon reading the generated PUF data sequence, correction code controller 122 can generate correction bits (e.g., parity bits, and so forth) utilizing a suitable error correction algorithm incorporated by correction code encoder 122. Once generated, the correction bits can be stored within PUF memory cells 112, in one or more disclosed embodiments (e.g., see FIGS. 3, 4, 7 and 7A, infra). Thus, as illustrated in FIG. 1, PUF memory cells 112 can include both identifier bits (e.g., the PUF data) as well as correction bits associated with the identifier bits (e.g., parity bits, or other correction algorithm bits).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Asnaashari into the device and/or method of Hung in a manner such that parity bits in the non-volatile memory device would be generated, (regarding claim 9) and stored in the non-volatile memory device. The motivation to do so would have been to control data errors pertaining to such data utilized for identifier data for identifying a chip (chip ID), a cryptographic key for security functions (see [0008] of Asnaashari).
Regarding claims 17-18: Hung does not specifically teach the controller further configured to generate parity bits associated with the output, (regarding claim 18) and to cause the parity bits to be stored in the data storage device.
Asnaashari ([0051]) teaches “Upon reading the generated PUF data sequence, correction code controller 122 can generate correction bits (e.g., parity bits, and so forth) utilizing a suitable error correction algorithm incorporated by correction code encoder 122. Once generated, the correction bits can be stored within PUF memory cells 112, in one or more disclosed embodiments (e.g., see FIGS. 3, 4, 7 and 7A, infra). Thus, as illustrated in FIG. 1, PUF memory cells 112 can include both identifier bits (e.g., the PUF data) as well as correction bits associated with the identifier bits (e.g., parity bits, or other correction algorithm bits).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Asnaashari into the device and/or method of Hung in a manner such that the controller would further be configured to generate parity bits associated with the output, (regarding claim 18) and to cause the parity bits to be stored in the data storage device. The motivation to do so would have been to control data errors pertaining to such data utilized for identifier data for identifying a chip (chip ID), a cryptographic key for security functions (see [0008] of Asnaashari).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 2020/0036539 A1) as modified by Ju (US 2022/0050608 A1), and further in view of Kim et al. (US 2015/0055417 A1; “Kim”).
Regarding claim 11: Hung does not specifically teach the first state is a state in which the plurality of memory cells are in a programmed state.
Kim (FIG. 3; [0065-0067]) teaches using a first state of a programmed state to implement an unclonable device in a manner similar to that of Hung, wherein a read voltage at the median of the distribution is used to divide the distribution.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kim into Hung in a manner such that the first state would be a state in which the plurality of memory cells are in a programmed state. The motivation to do so would have been to use another starting distribution of memory cells, namely a programmed state distribution, which was already known to be suitable for implementing a PUF as exemplified by Kim, to divide along a read threshold voltage approximately in the middle of the distribution to implement an unclonable device. Such a distribution would be simply an alternative range of threshold voltages suitable for dividing in a manner like that taught by Hung so as to implement an unclonable device.
Response to Arguments
Applicant’s arguments with respect to the pending claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
It is widely known in the art that a read operation is typically performed in a unit of a page, which means each memory cell of a page is read when reading the information stored in the page. The new reference of Ju is explicit in teaching the storing of a security key to a page of a memory and also teaches using a page as a unit of data when reading from or writing to a memory. Also, Examiner repeats that Hung [0072] already teaches the initial distribution of memory cells 500 in FIG. 4A is generated by a page erase operation. Hence, storing the security key of Hung in a single page and reading each of the memory cells in the stored page to obtain the security key and readout the security key by using the dividing line read threshold voltage in FIG. 4B already disclosed by Hung would have been obvious. FIG. 4C was disclosed by Hung to be an additional embodiment or technique (see “another technique” in [0079]) to compensate for voltage threshold drift that “some types of memory cells” (see [0077]) can have. Hence, FIG. 4C does not preclude FIG. 4B from being used on types of memory cells, different from the “some types of memory cells”, that are practical for being stable for a longer time and for being read as in FIG. 4B by using the dividing line threshold voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights