DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 20: Amended claim 20 is not definite as to whether the address is being stored in the processing means or is the address being stored in the non-volatile storage device by the processing means. For the purpose of examination, claim 20 will be interpreted as follows:
The non-volatile storage device of claim 19, wherein the processing means is further operable to store an address, associated with the at least one of the plurality of memory storage means, in the non-volatile storage device.
By adding the commas, it is now definite that an address is stored in the non-volatile storage device like in each of claim 7 and 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 10, 12-15, and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (US 2020/0036539 A1).
Regarding claim 1: Hung (a device in FIG. 1, FIG. 2, and FIG. 3 using method of FIG. 4A-C, FIG. 6, [0069-0080, 0089-0091] or FIG. 12A-C, FIG. 13, [0119-0127]) teaches a method for generating a random number using a non-volatile memory based physical unclonable function (PUF), comprising:
identifying a page of a memory die of a non-volatile memory device (“A device as described, for example, which is implemented in a single packaged integrated circuit or multichip module that comprises a non-volatile memory array including a plurality of blocks of memory cells with a security key stored in a particular block” is stated in [0016]; starting distribution 500 is established by using a page erase operation as stated in [0072]; hence, a page is identified);
causing a plurality of memory cells associated with the identified page to be in a first state (an erased state represented by starting distribution 500 in FIG. 4A or 1200 in FIG. 12A);
determining an initial read threshold voltage (a threshold voltage corresponding to the dividing line in FIG. 4B or read voltage VR in FIG. 12B is determined such as by using the steps in FIG. 6 or FIG. 8 or 13);
performing a soft read operation on the plurality of memory cells using the initial read threshold voltage, wherein the soft read operation using the initial read threshold voltage causes a subset of memory cells of the plurality of memory cells that are in the first state to be read as being in a second state, wherein the second state is different from the first state (as seen in FIG. 4B or FIG. 12B, for example, wherein cells in the initial distribution state that have a threshold voltage below the dividing line are read as being in a data “1” state and cells in the initial distribution state that have a threshold voltage above the dividing line are read as being a data “0”);
determining whether a number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to a number of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6 or 1330 in FIG. 13; see “it may be desirable that the ratio of zeros to ones be close to 1” in [0076]);
generating an output ([0017-0022]; an output data set that is a PUF-based data set; see step 260 in FIG. 6 or step 1370 of FIG. 13) based, at least in part, on determining that the number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to the number of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6 or step 1330 in FIG. 13; using a ratio of 1 in these steps as disclosed in [0076]); and
providing the output to a computing device (see “A PUF then provides or is used to provide a unique data set, which unique data set is accessible on a bus 131 by the security logic 125 through a PUF program controller 140 on bus 141, and utilized by the security logic in communications across line 122 with the access control block 115” in [0054-0057]; the data on either bus 141 or on bus 131 may be considered to be the output, and either one of 140 and 125 in FIG. 1 or both may be referred to as a computing device; also see output from 440 to processor system 410 in FIG. 2).
Regarding claim 2: Hung teaches the method of claim 1, wherein the output is a random number represented by the number of memory cells that are in the first state and are read as being in the second state and the number of memory cells that are in the first state and are read as being in the first state (FIG. 4B or FIG. 12B; see “random key” in [0011, 0182], “random keys” in [0015], see “random number in [0175] in regards to FIG. 27).
Regarding claim 3: Hung teaches the method of claim 1, further comprising determining a second read threshold voltage based on determining that the number of memory cells that are in the first state and are read as being in the second state is substantially higher or substantially lower than the number of memory cells that are in the first state and are read as being in the first state (see 240 in FIG. 6 or 1340 in FIG. 13).
Regarding claim 4: Hung teaches the method of claim 3, further comprising:
performing a subsequent soft read operation on the plurality of memory cells using the second read threshold voltage, wherein the subsequent soft read operation using the second read threshold voltage causes a second subset of memory cells of the plurality of memory cells that are in the first state to be read as being in a second state that is different from the first state (performing 210 at a time after performing 240 in FIG. 6 or performing 1310 after performing 1340 in FIG. 13); and
determining whether a number of memory cells in the second subset of memory cells that are in the first state and are read as being in the second state is substantially equivalent to a number of memory cells in the second subset of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6 after another iteration of 210 or step 1330 in FIG. 13 after another iteration of 1310).
Regarding claim 5: Hung teaches the method of claim 4, further comprising:
generating the output based, at least in part, on determining that the number of memory cells in the second subset of memory cells that are in the first state and are read as being in the second state is substantially equivalent to the number of memory cells in the second subset of memory cells that are in the first state and are read as being in the first state (260 in FIG. 6 or 1370 in FIG. 13; using a ratio of 1 as disclosed in [0076]); and
providing the output to the computing device (see “A PUF then provides or is used to provide a unique data set, which unique data set is accessible on a bus 131 by the security logic 125 through a PUF program controller 140 on bus 141, and utilized by the security logic in communications across line 122 with the access control block 115” in [0054-0057]; the data on either bus 141 or on bus 131 may be considered to be the output, and either one of 140 and 125 in FIG. 1 or both may be referred to as a computing device; also see output from 440 to processor system 410 in FIG. 2).
Regarding claim 6: Hung teaches the method of claim 1, wherein identifying the page of the memory die comprises identifying an address of the identified page (since “a page erase operation” in [0072] inherently requires identifying a page to erase by an address then Hung’s invention inherently identifies an address of the page in order to perform the page erase operation).
Regarding claim 10: Hung teaches the first state is a state in which the plurality of memory cells are in an erased state (see “a page erase operation” in [0072]).
Regarding claim 12: Hung (a device in FIG. 1, FIG. 2, and FIG. 3 using method of FIG. 4A-C, FIG. 6, [0069-0080, 0089-0091] or FIG. 12A-C, FIG. 13, [0119-0127]) teaches a data storage device, comprising:
at least one memory die (see “multichip module” in 0016] or “system-on-a-chip SOC” in [0053-0054]); and
a controller (125 and 140 in FIG. 1, [0054-0057] or processor system 410 in FIG. 2, [0061]) communicatively coupled to the at least one memory die and configured to:
identify a page of the at least one memory die (“A device as described, for example, which is implemented in a single packaged integrated circuit or multichip module that comprises a non-volatile memory array including a plurality of blocks of memory cells with a security key stored in a particular block” is stated in [0016]; starting distribution 500 is established by using a page erase operation as stated in [0072]; hence, a page is identified);
cause a plurality of memory cells associated with the identified page to be in a first state (starting distribution 500 in FIG. 4A or 1200 in FIG. 12A);
determine an initial read threshold voltage (a threshold voltage corresponding to the dividing line in FIG. 4B or read voltage VR in FIG. 12B);
perform a soft read operation on the plurality of memory cells using the initial read threshold voltage, wherein the soft read operation using the initial read threshold voltage causes a subset of memory cells of the plurality of memory cells that are in the first state to be read as being in a second state that is different from the first state (as seen in FIG. 4B or FIG. 12B, for example, wherein cells in the initial distribution state that have a threshold voltage below the dividing line are read as being in a data “1” state and cells in the initial distribution state that have a threshold voltage above the dividing line are read as being a data “0”);
determine whether a number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to a number of memory cells that are in the first state and are read as being in the first state (step 230 in FIG. 6 or 1330 in FIG. 13 using a ratio of 1; see “it may be desirable that the ratio of zeros to ones be close to 1” in [0076]); and
generate an output (see “A PUF then provides or is used to provide a unique data set, which unique data set is accessible on a bus 131 by the security logic 125 through a PUF program controller 140 on bus 141, and utilized by the security logic in communications across line 122 with the access control block 115” in [0054-0057]; the data on either bus 141 or on bus 131 may be considered to be the output, and either one of 140 and 125 in FIG. 1 or both may be referred to as a computing device; also see output from 440 to processor system 410 in FIG. 2) based, ate least in part, on a determination that the number of memory cells that are in the first state and are read as being in the second state is substantially equivalent to the number of memory cells that are in the first state and are read as being in the first state (see step 260 in FIG. 6 or step 1370 in FIG. 13).
Regarding claim 13: Hung teaches the controller is further configured to provide the output to a computing device (either one of 140 and 125 in FIG. 1 or both may be referred to as a computing device; Also, see “The output data set can be provided to an external system, such as the system controlling execution of the PUF for use as a shared secret in a security protocol” in [0091] and “The output data set can be provided to an external system, such as the system controlling execution of the PUF for use as a shared secret in a security protocol.“ in [0126]).
Regarding claim 14: Hung teaches claim 12, wherein the output is a random number represented by the number of memory cells that are in the first state and are read as being in the second state and the number of memory cells that are in the first state and are read as being in the first state (FIG. 4B or FIG. 12B; see “random key” in [0011, 0182], “random keys” in [0015], see “random number in [0175] in regards to FIG. 27).
Regarding claim 15: Hung teaches claim 12, wherein identifying the page of the memory die comprises identifying an address of the identified page (since “a page erase operation” in [0072] inherently requires identifying a page to erase by an address then Hung’s invention inherently identifies an address of the page in order to perform the page erase operation).
Regarding claim 19: Hung (a device in FIG. 1, FIG. 2, and FIG. 3 using method of FIG. 4A-C, FIG. 6, [0069-0080, 0089-0091] or FIG. 12A-C, FIG. 13, [0119-0127]) teaches a non-volatile storage device, comprising:
a plurality of storage means (memory cells in a “multichip module” in [0016] or “system-on-a-chip SOC” in [0052-0060]);
processing means (either one of 140 and 125 in FIG. 1 or both) operable to:
cause a plurality of memory means (PUF memory cells in Flash Memory Array 130) associated with at least one of the plurality of memory storage means to be in a first state (starting distribution 500 in FIG. 4A or 1200 in FIG. 12A);
perform a soft read operation on the plurality of memory means (cells) using an initial read threshold voltage, wherein the soft read operation using the initial read threshold voltage causes a subset of memory means of the plurality of memory means that are in the first state to be read as being in a second state that is different from the first state (as seen in FIG. 4B or FIG. 12B, for example, wherein cells in the initial distribution state that have a threshold voltage below the dividing line are read as being in a data “1” state and cells in the initial distribution state that have a threshold voltage above the dividing line are read as being a data “0”);
determine whether a number of memory means that are in the first state and are read as being in the second state is substantially equivalent to a number of memory means that are in the first state and are read as being in the first state (step 230 in FIG. 6 or 1330 in FIG. 13; see “it may be desirable that the ratio of zeros to ones be close to 1” in [0076]); and
generate an output ([0017-0022]; an output data set that is a PUF-based data set; see step 260 in FIG. 6 or step 1370 of FIG. 13) based, at least in part, on a determination that the number of memory means that are in the first state and are read as being in the second state is substantially equivalent to the number of memory means that are in the first state and are read as being in the first state (step 230 in FIG. 6 or step 1330 in FIG. 13; using a ratio of 1 in these steps as disclosed in [0076]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 2020/0036539 A1) in view of Kim et al. (US 2015/0055417 A1).
Regarding claim 11: Hung does not specifically teach the first state is a state in which the plurality of memory cells are in a programmed state.
Kim (FIG. 3; [0065-0067]) teaches using a first state of a programmed state to implement an unclonable device in a manner similar to that of Hung, wherein a read voltage at the median of the distribution is used to divide the distribution.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kim into Hung in a manner such that the first state would be a state in which the plurality of memory cells are in a programmed state. The motivation to do so would have been to use another starting distribution of memory cells, namely a programmed state distribution, which was already known to be suitable for implementing a PUF as exemplified by Kim, to divide along a read threshold voltage approximately in the middle of the distribution to implement an unclonable device. Such a distribution would be simply an alternative range of threshold voltages suitable for dividing in a manner like that taught by Hung so as to implement an unclonable device.
Claim(s) 7, 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 2020/0036539 A1) in view of Fujita et al. (US 2021/0303182 A1).
Regarding claim 7: Hung does not specifically teach storing the address of the identified page in the non-volatile memory device.
Fujita ([0032-0033]; FIG. 5A) teaches generating a random sequence as part of implementing a NAND PUF in a manner similar to that taught by Hung, wherein a page of memory cells in a memory array having a threshold voltage distribution is divided by a using a read threshold voltage approximately in the middle of the distribution, and the address of the stored random sequence may be stored on the NAND flash memory chip itself., for example, in another page of the NAND flash memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fujita into Hung in a manner such that the address of the identified page would be stored in the non-volatile memory device. The motivation to do so would have been to store the page address of the random number so that the random number may be read to determine key needed to enable access to data, or to decrypt or encrypt data, stored in the blocks in the plurality of blocks (see [0016] of Hung).
Regarding claim 16: Hung does not specifically teach the controller is further configured to cause the address of the identified page to be stored in the data storage device.
Fujita ([0032-0033]; FIG. 5A) teaches generating a random sequence as part of implementing a NAND PUF in a manner similar to that taught by Hung, wherein a page of memory cells in a memory array having a threshold voltage distribution is divided by a using a read threshold voltage approximately in the middle of the distribution, and the address of the stored random sequence may be stored on the NAND flash memory chip itself., for example, in another page of the NAND flash memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fujita into Hung in a manner such that the controller would be further configured to cause the address of the identified page to be stored in the data storage device like that taught by Fujita. The motivation to do so would have been to store the page address of the random number so that the random number may be read to determine key needed to enable access to data, or to decrypt or encrypt data, stored in the blocks in the plurality of blocks (see [0016] of Hung).
Regarding claim 20: In so far as definite, Hung does not specifically teach the non-volatile storage device of claim 19, wherein the processing means is further operable to store an address[,] associated with the at least one of the plurality of memory storage means[,] in the non-volatile storage device.
Fujita ([0032-0033]; FIG. 5A) teaches generating a random sequence as part of implementing a NAND PUF in a manner similar to that taught by Hung, wherein a page of memory cells in a memory array having a threshold voltage distribution is divided by a using a read threshold voltage approximately in the middle of the distribution, and the address of the stored random sequence may be stored on the NAND flash memory chip itself, for example, in another page of the NAND flash memory chip.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Fujita into Hung in a manner such that the address of the identified page would be stored in the non-volatile memory device like that taught by Fujita by the controller, such as stored into another page of the memory array. The motivation to do so would have been to store the page address of the random number so that the random number may be read to determine the key needed to enable access to data, or to decrypt or encrypt data, stored in the blocks in the plurality of blocks (see [0016] of Hung).
Claim(s) 8-9 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 2020/0036539 A1) in view of Asnaashari (US 20230317158 A1).
Regarding claims 8-9: Hung does not specifically teach generating parity bits in the non-volatile memory device, (regarding claim 9) and storing the parity bits in the non-volatile memory device.
Asnaashari ([0051]) teaches “Upon reading the generated PUF data sequence, correction code controller 122 can generate correction bits (e.g., parity bits, and so forth) utilizing a suitable error correction algorithm incorporated by correction code encoder 122. Once generated, the correction bits can be stored within PUF memory cells 112, in one or more disclosed embodiments (e.g., see FIGS. 3, 4, 7 and 7A, infra). Thus, as illustrated in FIG. 1, PUF memory cells 112 can include both identifier bits (e.g., the PUF data) as well as correction bits associated with the identifier bits (e.g., parity bits, or other correction algorithm bits).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Asnaashari into the device and/or method of Hung in a manner such that parity bits in the non-volatile memory device would be generated, (regarding claim 9) and stored in the non-volatile memory device. The motivation to do so would have been to control data errors pertaining to such data utilized for identifier data for identifying a chip (chip ID), a cryptographic key for security functions (see [0008] of Asnaashari).
Regarding claims 17-18: Hung does not specifically teach the controller further configured to generate parity bits associated with the output, (regarding claim 18) and to cause the parity bits to be stored in the data storage device.
Asnaashari ([0051]) teaches “Upon reading the generated PUF data sequence, correction code controller 122 can generate correction bits (e.g., parity bits, and so forth) utilizing a suitable error correction algorithm incorporated by correction code encoder 122. Once generated, the correction bits can be stored within PUF memory cells 112, in one or more disclosed embodiments (e.g., see FIGS. 3, 4, 7 and 7A, infra). Thus, as illustrated in FIG. 1, PUF memory cells 112 can include both identifier bits (e.g., the PUF data) as well as correction bits associated with the identifier bits (e.g., parity bits, or other correction algorithm bits).”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Asnaashari into the device and/or method of Hung in a manner such that the controller would further be configured to generate parity bits associated with the output, (regarding claim 18) and to cause the parity bits to be stored in the data storage device. The motivation to do so would have been to control data errors pertaining to such data utilized for identifier data for identifying a chip (chip ID), a cryptographic key for security functions (see [0008] of Asnaashari).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights