Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Su states “[t]aking advantage that not all solder balls are electrically connected, i.e., not connected (NC) pins, and some solder balls share the same function, a plurality of solder balls can be combined to form a larger solder island in accordance with the teachings of the present invention.” 3:57-61. The statement necessarily implies that some solder balls share the same function, then some must share different functions, satisfying the amended limitation “different types” of signal pins. Stated most simply, the person of ordinary skill having the benefit of Su can readily electrically connect (associate) any of the solder bars or balls with any I/O, power, ground, etc. as applications require.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the masking means must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
In Claim 20, “masking means” is understood to be a solder mask [0051, 0063-0064].
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. The claim has been limited to “…substrate, at least one solder bar of the plurality of solder bars being associated with a first signal pin of a first type and a second signal pin of a second type that is different from the first type…” which is not readily able to be understood. As drafted, the limitation causes a single solder bar to be shorted to two different signal pins, which is likely not what was intended. Based on the specification, it appears what was intended was “…substrate, at least one solder bar of the plurality of solder bars being associated with a first signal pin of a first type and another of the plurality of solder bars being associated with a second signal pin of a second type that is different from the first type…” The claim will be interpreted as such for purposes of examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. No. 9560771 to Su et al. (Su) or alternatively over Su in view of U.S. Pat. Pub. No . 20160066439 to Ando et al. (Ando).
Regarding Claim 1, Su teaches an integrated circuit, comprising:
a substrate 304; and
a grid 330 of connection points disposed on a surface of the substrate, the grid of connection points comprising:
a first connection point type 302 having a first structure; and
a second connection point type 310 having a second structure that is different from the first structure, the second connection point type being disposed on a perimeter of the substrate (see Fig. 3D for example).
Su does not explicitly teach the first connection point type being associated with a single signal pin and the second connection point type associated with different types signal pins. Su does state however that “[t]aking advantage that not all solder balls are electrically connected, i.e., not connected (NC) pins, and some solder balls share the same function, a plurality of solder balls can be combined to form a larger solder island in accordance with the teachings of the present invention.” 3:57-61.
The person of ordinary skill having the benefit of Su may readily connect any solder balls to any signal, satisfying the limitation. It would therefore have been obvious to the person of ordinary skill in the art before the time of filing to modify Su according to application specific requirements.
Alternatively, Ando states that “individual signal input functions and/or signal output functions are assigned to any of the solder balls 32a of the semiconductor package 32, for example, one by one [0062].” It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Ando to complete the teaching of Su by enabling the person of ordinary skill to wire an IC package up as applications require.
Regarding Claim 2, Su and Ando teach the integrated circuit of claim 1, wherein the first connection point type is a solder ball and the second connection point type is a solder bar (see Figs. 3D and 4B; round pads 302 become solder balls 402 and elongated pads 310 become solder bars 410 upon reflow).
Regarding Claim 3, Su and Ando teach the integrated circuit of claim 1, wherein multiple second connection point types are disposed around the perimeter of the substrate and wherein at least one first connection point type is disposed around the perimeter between the multiple second connection point types (see Fig. 3D, individual balls 302 between bars 310).
Regarding Claim 4, Su and Ando teach the integrated circuit of claim 1, wherein a height of the first connection point type is substantially equivalent to a height of the second connection point type 4:5-8.
Regarding Claim 5, Su and Ando teach the integrated circuit of claim 1, wherein the single signal pin and the multiple signal pins are selected from a group comprising: a ground pin; a no-connect pin; and a non-critical pin (the person of ordinary skill may readily select ground pins to be combined into a bar to maintain a same reference level and greater current carrying capability, see also 3:58).
Regarding Claim 6, Su and Ando teach the integrated circuit of claim 1, wherein the single signal pin is selected from a group comprising: a power pin; a data pin; a control pin; and a clock pin (the person of ordinary skill may readily select I/O function according to application specific requirements).
Regarding Claim 7, Su and Ando teach the integrated circuit of claim 1, wherein the integrated circuit is coupled to a printed circuit board and wherein the printed circuit board comprises copper pads that at least substantially match a shape and a layout of the first connection point type and a shape and a layout of the second connection point type disposed on the substrate (4:21-23; although Su does not explicitly teach copper pads and is silent as to the contact material, the person of ordinary skill would be motivated to use copper as it is the most common, well known and understood material for PCB traces).
Regarding Claim 8, Su and Ando teach an integrated circuit, comprising:
a substrate; and
a grid of connection points disposed on a surface of the substrate, the grid of connection points comprising:
a plurality of solder bars disposed around a perimeter of the substrate, at least one solder bar of the plurality of solder bars being associated with a first signal pin of a first type and another of the plurality of solder bars being associated with a second signal pin of a second type that is different from the first type (see above, the person of ordinary skill can wire up a ball/bar grid array for application specific requirements);
a first plurality of solder balls disposed around the perimeter of the substrate, wherein at least one solder ball of the plurality of solder balls is disposed between a first solder bar of the plurality of solder bars and a second solder bar of the plurality of solder balls; and
a second plurality of solder balls disposed within the perimeter of the substrate (see rejections of claims 1-3 above, Figs. 3D and 4B).
Regarding Claim 9, Su and Ando teach the integrated circuit of claim 8, wherein each solder ball of the first plurality of solder balls and each solder ball of the second plurality of solder balls are associated with a single signal pin (see rejection of Claim 2 above).
Regarding Claim 10, Su and Ando teach the integrated circuit of claim 9, wherein the single signal pin and the at least two signal pins are selected from a group comprising: a ground pin; a no-connect pin; and a non-critical pin (see rejection of Claim 5 above, see also grid array of Ando in Fig. 5).
Regarding Claim 11, Su and Ando teach the integrated circuit of claim 9, wherein the single signal pin is selected from a group comprising: a power pin; a data pin; a control pin; and a clock pin (see rejection of Claim 6 above).
Regarding Claim 12, Su and Ando teach the integrated circuit of claim 8, wherein the integrated circuit is coupled to a printed circuit board and wherein the printed circuit board comprises copper pads that at least substantially match a shape and a layout of the plurality of solder bars and a shape and layout of the first plurality of solder balls and the second plurality of solder balls (see rejection of Claim 7 above).
Regarding Claim 13, Su and Ando teach the integrated circuit of claim 8, further comprising a solder mask that causes a height of each of the plurality of solder bars to be substantially equivalent to a height of each of the first plurality of solder balls and to a height of each of the second plurality of solder balls (see rejection of Claim 4 above).
Regarding Claim 14, Su teaches a grid of connection points for electrically coupling a first computing component to a second computing component, comprising: a first connection means having a first structure and being associated with a single signal means; and a second connection means having a second structure that is different from the first structure and being associated with multiple signal means of different types, the second connection means being disposed on a perimeter of the first computing component (see rejection of Claims 1 and 5 above at least, see also 2:44-45 teaching that the IC may be combinational logic which is a computing component, and further the person of ordinary skill having the benefit of Suh may arrange the I/O to meet application specific requirements).
Regarding Claim 15, Su teaches the grid of connection points of claim 14, wherein the first connection means is a solder ball and the second connection means is a solder bar (see the rejection of Claim 2 above).
Regarding Claim 16, Su teaches the grid of connection points of claim 14, wherein multiple second connection means are disposed around the perimeter of the first computing component and wherein at least one first connection means is disposed around the perimeter of the first computing component between the multiple second connection means (see Fig. 3D).
Regarding Claim 17, Su teaches the grid of connection points of claim 14, wherein the single signal means and the multiple signal means are selected from a group comprising: a ground signal means; a no-connect signal means; and a non-critical signal means (see above).
Regarding Claim 18, Su teaches the grid of connection points of claim 14, wherein the single signal means is selected from a group comprising: a power signal means; a data signal means; a control signal means; and a clock signal means (see above).
Regarding Claim 19, Su teaches the grid of connection points of claim 14, wherein the second computing component is a printed circuit board that comprises a third connection means, the third connection means having one or more shapes and a layout that substantially match a shape and layout of the first connection means and a shape and a layout of the second connection means disposed on the first computing component (see above, it would further be obvious for the pads on the PCB to match the shape of the connection points to maximize electrical contact and enhance structural rigidity).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 14 above, and further in view of U.S. Pat. No. 6133134 to Mehr.
Regarding Claim 19, Su teaches the grid of connection points of claim 14, but does not explicitly teach a masking means that causes a height of the first connection means to be substantially equivalent to a height of the second connection means.
However, in analogous art, Mehr teaches a solder mask 32 for maintaining a height of solder balls 34. It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Mehr since Su explicitly suggests maintaining a height of the solder balls.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EVREN SEVEN/Primary Examiner, Art Unit 2812