Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claims 1-13, 18-20 are objected to because of the following informalities:
Claim 1, 2, 6, 13 and 18 presently recites the limitation “the signal lines” and “the source lines”. There are insufficient antecedent basis for this limitation in the claim.
For the purpose of the examination, the limitation will be interpreted as “the plurality of signal lines” in line 5 and “the plurality of source lines”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pat # 10957394).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Chen et al. teach a non-volatile storage apparatus, comprising: non-volatile memory cells arranged in groups; a plurality of source lines connected to the memory cells; the plurality of source lines are electrically isolated from each other; a plurality of signal lines positioned between the groups, the signal lines are configured to apply a source voltage to the source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10, lines 42-47, column 24 lines 1-3 where memory array divide into block BLK0…BLK7, decoder 124, driver 340, 330 are coupled to bitline and P-weel, unit 331 is source line driver to apply voltage to source line, In Fig. 3, 5, 6, page 12, lines 39-41, Page 14, lines 42-49 Chen et al. teach that source line (SL) voltage driver 331 provides source voltage Vsl for each block via local interconnect 651. Also, the interconnect line 651 is surrounded by insulating layer 651a); isolation layers between the signal lines to isolate the signal lines from each other; and a control circuit connected to the non-volatile memory cells and the signal lines (interconnect line 651 is surrounded by insulating layer 651a), the control circuit is configured to program the memory cells by perform hole pre-charging followed by boosting and applying a program voltage, the control circuit is configured to performing hole pre-charging by applying the source voltage to a selected source line of the plurality of source lines for a selected group via a selected signal line of the plurality of signal lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10, lines 42-47, column 24 lines 1-3 where unit 110 is control circuitry, pre-charging using holes for channel boost at step 1102, 1433a).
Even though Chen et al. teach about dielectric layers and insulating layer 651a between lines but silent exclusively about isolation layer. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Chen et al. where dielectric layer is actually non-conductive layer between metal lines / signal lines which would be called isolation layer in order to develop cost scalable memory structure (see column 1 lines 21-23).
Regarding claim 2, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: each source line of the plurality of source lines is connected to a subset of the groups and each group is connected to one of the source lines; and the isolation layers are positioned between source lines to isolate the source lines from each other (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10).
Regarding claim 3, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: the source voltage is greater in magnitude than any predetermined threshold voltage of an erased threshold voltage distribution for the memory cells (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22).
Regarding claim 4, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: the source voltage is more than double in magnitude than any predetermined threshold voltage of an erased threshold voltage distribution for the memory cells (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67).
Regarding claim 5, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: the applying the source voltage to the selected signal line charges up only the selected source line and does not charge up all other source lines of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-50).
Regarding claim 6, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: each group is a block of memory cells; each source line of the plurality of source lines is connected to a subset of the blocks and each block is connected to one of the source lines; and each signal line of the plurality of signal lines is positioned between two blocks and connected to one source line of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10).
Regarding claim 7, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: each group is a block of memory cells; each source line of the plurality of source lines is connected to two of the blocks and each block is connected to one of the source lines; and each signal line of the plurality of signal lines is positioned between two blocks and connected to one source line of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22).
Regarding claim 8, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: each group is a block of memory cells (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67).
Regarding claim 9, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: each group is a block of memory cells; and the memory cells are arranged as NAND strings in the blocks (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-50).
Regarding claim 10, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: the non-volatile memory cells are arranged as NAND strings having a source end and a bit line end; and the control circuit is configured to performing hole pre-charging by pre-charging from the source end (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67).
Regarding claim 11, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Chen et al. further teach, wherein: the control circuit is configured to program the memory cells in a word line order in the direction from the bit line end to the source end (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10).
Regarding claim 12, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: the apparatus further comprises word lines connected to the memory cells; each group is a block of memory cells; the memory cells are arranged as NAND strings in the blocks; the NAND strings include a source end and a bit line end; each block of memory cells is divided into sub-blocks that can be independently erased and programmed; and the control circuit is configured to program the memory cells within a sub-block in a word line order in the direction from the bit line end to the source end (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51).
Regarding claim 13, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Chen et al. further teach, wherein: each group is a block of memory cells; the memory cells are arranged as NAND strings in the blocks; the source voltage is greater in magnitude than any predetermined threshold voltage of an erased threshold voltage distribution for the memory cells; the applying the source voltage to the selected source line charges up only the selected source line and does not charge up all other source lines of the plurality of source lines; each source line of the plurality of source lines is connected to a subset of the blocks and each block is connected to one of the source lines; each signal line of the plurality of signal lines is positioned between two blocks (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-50) and connected to one source line of the plurality of source lines; and the control circuit is configured to program memory cells of a selected block by performing hole pre-charging of channels of unselected NAND strings in the selected block followed by boosting channels of unselected NAND strings in the selected block and applying a program voltage to selected NAND strings in the selected block (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67).
Regarding independent claim 14, Chen et al. teach a method for programming memory cells from an erased threshold voltage distribution to one or more programmed threshold voltage distributions, comprising: performing hole pre-charging of channels of unselected NAND strings in a selected block of a selected plane including applying a source voltage to a selected signal line of a plurality of signal lines that are isolated from each other and are connected to the plane (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10, lines 42-47, column 24 lines 1-3 where each string coupled to bit line, 1201..1206 are program voltage distribution), the selected signal line is positioned between the selected block and an unselected block and is connected to a selected source line of a plurality of source lines, the plurality of source lines are connected to the plane such that the selected source line is connected to the selected block, the source voltage is greater in magnitude than any predetermined threshold voltage of the erased threshold voltage distribution; and after the pre-charging, boosting channels of unselected NAND strings in the selected block and applying a program voltage to selected NAND strings in the selected block (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10, lines 42-47, column 24 lines 1-3 where unit 110 is control circuitry, pre-charging using holes for channel boost, source line SL voltage driver 330 provide voltage Vsl, hole-type precharging at step 1102, 1433a).
Even though Chen et al. teach about dielectric layers between signal lines but silent exclusively about isolated from each other. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Chen et al. where dielectric layer is actually non-conductive layer between metal lines / signal lines which is isolated from each other in order to develop cost scalable memory structure (see column 1 lines 21-23).
Regarding claim 15, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Chen et al. further teach, wherein: the applying the source voltage to the selected signal line charges up only the selected source line and does not charge up all other source lines of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-45).
Regarding claim 16, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Chen et al. further teach, wherein: the selected block is divided into sub-blocks; the method further comprises independently erasing and programming the sub-blocks of the selected block, including programming memory cells within a sub-block in a word line order in the direction from a bit line to the selected source line; the performing hole pre-charging of channels of unselected NAND strings comprises pre-charging from the selected source line; and the applying the source voltage to the selected signal line charges up only the selected source line and does not charge up all other source lines of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67).
Regarding claim 17, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Chen et al. further teach, wherein: each source line of the plurality of source lines is connected to a subset of blocks and each block is connected to one of the source lines; and each signal line of the plurality of signal lines is positioned between two blocks and connected to one source line of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-35).
Regarding independent claim 18, Chen et al. teach a non-volatile storage apparatus, comprising: non-volatile memory cells arranged as NAND strings in blocks; a plurality of source lines connected to the memory cells such that each source line is connected to a subset of the blocks and each block is connected to one of the source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10, lines 42-47, column 24 lines 1-3 where memory array divide into block BLK0…BLK7, decoder 124, driver 340, 330 are coupled to bitline and P-weel, unit 331 is source line driver to apply voltage to source line, in Fig. 3, 5, 6, page 12, lines 39-41, Page 14, lines 42-49, Chen et al. teach that source line (SL) voltage driver 331 provides source voltage Vsl for each block via local interconnect 651. Also, the interconnect line 651 is surrounded by insulating layer 651a); a plurality of signal lines positioned between the blocks; isolation layers between the source lines to isolate the source lines from each other; and a control circuit connected to the non-volatile memory cells and the signal lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10, lines 42-47), the control circuit includes one or more voltage sources, the signal lines are connected to the one or more voltage sources and are connected to the source lines for applying voltage from the one or more voltage sources to the source lines, the control circuit is configured to program memory cells of a selected block by performing hole pre-charging of channels of unselected NAND strings in the selected block followed by boosting channels of unselected NAND strings in the selected block and applying a program voltage to selected NAND strings in the selected block, the control circuit is configured to perform hole pre-charging by applying a source voltage to a selected source line of the plurality of source lines for a selected block via a selected signal line of the plurality of signal lines, the source voltage is greater in magnitude than any predetermined threshold voltage of an erased threshold voltage distribution for the memory cells (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10, lines 42-47, column 24 lines 1-3 where unit 110 is control circuitry, pre-charging using holes for channel boost, source line SL voltage driver 330 provide voltage Vsl, hole-type precharging at step 1102, 1433a).
Even though Chen et al. teach about dielectric layers between lines but silent exclusively about isolation layer. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Chen et al. where dielectric layer is actually non-conductive layer between metal lines / signal lines which would be called isolation layer in order to develop cost scalable memory structure (see column 1 lines 21-23).
Regarding claim 19, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Chen et al. further teach, wherein: the apparatus further comprises word lines connected to the memory cells; the NAND strings include a source end and a bit line end; each block of memory cells is divided into sub-blocks that can be independently erased and programmed; the control circuit is configured to program the memory cells within a sub-block in a word line order in the direction from the bit line end to the source end; the control circuit is configured to performing hole pre-charging by pre-charging from the source end; and the applying the source voltage to the selected signal line charges up only the selected source line and does not charge up all other source lines of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-60).
Regarding claim 20, Chen et al. teach all claimed subject matter as applied in prior rejection of claim 18 on which this claim depends.
Chen et al. further teach, wherein: each source line of the plurality of source lines is connected to a subset of the blocks and each block is connected to one of the source lines; and each signal line of the plurality of signal lines is positioned between two blocks and connected to one source line of the plurality of source lines (see Fig. 1A, 3-4, 6-16 and column 3 lines 51-67, column 4 lines 1-67, column 5 lines 1-40, column 11 lines 40-67, column 12 lines 1-64, column 13 lines 40-67, column 14 lines 1-56, column 15-18, column 19 lines 1-51, column 20 lines 32-67, column 21-22, column 23 lines 1-10).
Response to Arguments
Applicant's arguments filed 01/12/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 12 of remarks) that "the cited prior art references, alone or in combination, do not teach or suggest all of the limitations recited in the claims ". Examiner respectfully disagrees with this statement.
The limitation in claim 1 recite “a plurality of source lines connected to the memory cells, the plurality of source lines are electrically isolated from each other, a plurality of signal lines positioned between the groups, the signal lines are configured to apply a source voltage to the source lines.”
First, source lines can be interpreted as either local or global source line as the claim limitation didn’t specify. Similarly, signal lines can be interpreted as either local or global signal line as the claim limitation didn’t specify.
Second, the limitation “electrically isolated from each other” would be interpreted as no direct current flow between them.
In Fig. 3, 5, 6, page 12, lines 39-41, Page 14, lines 42-49 Chen et al. teach that source line (SL) voltage driver 331 provides source voltage Vsl for each block via local interconnect 651. Also, the interconnect line 651 is surrounded by insulating layer 651a. This clearly indicate that local signal lines (651) which receives source voltage are isolated from each other due to insulating layer 651a and each source line for each block also isolated.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824