DETAILED ACTION
Claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/24/23 is filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4-12, 14-16, 19, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al., U.S. Publication No. 2022/0020701.
Regarding claim 1, Ko discloses:
A semiconductor package, comprising (Fig. 2):
a lower part having a first region and a second region horizontally offset from one another, the lower part including a connection structure 110 within the first region and a logic chip 100 within the second region (110 and 100 representing the first and second regions, respectively, are offset from each other).
a memory structure 20 [0019] that overlaps the connection structure in a vertical direction, and
a thermal radiation structure (600 + 700), that overlaps the logic chip in the vertical direction, wherein the logic chip and the memory structure are spaced apart in a horizontal direction parallel to a top surface of the logic chip (100 and 20 are spaced apart from each other in the horizontal direction which is parallel to the top surface of the chip 100).
Regarding claim 2, Ko discloses the lower part further includes a pad layer 119 on the connection structure and the logic chip, the package further comprises a pad solder (Fig. 2) between the pad layer and the memory structure, and the pad layer includes a conductive pad that electrically connects the connection structure and the pad solder to each other (Figs. 2-3).
Regarding claim 4, Ko discloses (Fig. 3) wherein the connection includes a through connector, wherein the through connector includes: a first connector 511, a second connector 150, a third connector 115, a fourth connector 113, a fifth connector 117.
Regarding claim 5, Ko discloses:
wherein a width of the third connector 115 is greater than a width of an upper portion of the second connector 150, and a width of an upper portion of the fourth connector 113 is less than a width of the firth connector 117 and greater than a width of a lower portion of the fourth connector 113 (Fig. 3).
Regarding claim 6, Ko discloses wherein the width of the second connector decreases in a direction from top to bottom portions of the second connector (Fig. 3).
Regarding claim 7, Ko discloses wherein the thermal radiation structure includes or is composed of copper [0036].
Regarding claim 8, Ko discloses wherein the thermal radiation structure 700 completely overlaps the logic chip 100 in the vertical direction, and a width of the thermal radiation structure is greater than a width of the logic chip in the horizontal direction (Fig. 2).
Regarding claim 9, Ko discloses wherein the lower part further includes: a redistribution substrate that includes a redistribution pattern, and a connection solder between the connection structure and the redistribution pattern of the redistribution substrate [0023].
Regarding claim 10, Ko discloses:
A semiconductor package, comprising (Fig. 2):
a lower part having a first region and a second region horizontally offset from one another, the lower part including a connection structure 110 within the first region and a logic chip 100 within the second region.
a memory structure 20 that overlaps the connection structure in a vertical direction, and
a thermal radiation structure (600 + 700) on the second region and overlapping the semiconductor chip in the vertical direction, wherein the connection structure and the thermal radiation structure do not overlap each other in the vertical direction (Fig. 2, at least part of the thermal radiation 600 + 700 structure does not overlap connection structure 110 in the vertical direction).
Regarding claim 11, Ko discloses (Fig. 3) wherein the connection includes a through connector, wherein the through connector includes: a first connector 511, a second connector 150, a third connector 115, a fourth connector 113, a fifth connector 117, wherein a width of the third connector 115 is greater than a width of an upper portion of the second connector 150, and a width of an upper portion of the fourth connector 113 is less than a width of the firth connector 117 and greater than a width of a lower portion of the fourth connector 113 (Fig. 3).
Regarding claim 12, Ko discloses wherein the thermal radiation structure 700 completely overlaps the logic chip 100 in the vertical direction, and a width of the thermal radiation structure is greater than a width of the logic chip in the horizontal direction (Fig. 2).
Regarding claim 14, Ko discloses wherein the thermal conductivity of the thermal radiation (copper) is greater than a thermal conductivity of the chip.
Regarding claim 15, Ko discloses the lower part further includes a redistribution substrate and the package further comprises a passive element (in substrate 111) [0021].
Regarding claim 16, Ko discloses wherein the lower part further includes a connection solder between the redistribution substrate and the connection structure and the redistribution substrate (the layer that includes connection line 117) and the connection structure are electrically connected to each other through the connection solder ([0023], Fig. 2).
Regarding claim 19, Ko discloses the connection structure includes a lower connection dielectric layer, and a bottom surface of the lower connection dielectric layer (the layer where connections are embedded, Fig. 3) is at a vertical lever lower than bottom surface of the chip (the chip is on top of the connection structure, therefore the connection dielectric layer is lower than the bottom surface of the chip, Fig. 2).
Regarding claim 20, Ko discloses a lower part including a redistribution substrate (the substrate in Fig. 2, the other parts not considered 110, [0023, 0041]), a connection structure 110, and a semiconductor chip 100, the connection structure and the chip being electrically connected to the redistribution substrate [0023, 0041],
a memory structure 20 that overlaps the connection structure 110 in a vertical direction,
a thermal radiation structure 700 that overlaps an entirety of the chip in vertical direction,
wherein a width of the thermal radiation structure is greater than a width of the chip in a horizontal direction (Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al., U.S. Publication No. 2022/0020701, in view of Kwon, U.S. Publication No. 2019/0348340.
Regarding claims 3, 13, Ko fails to disclose the thermal radiation structure wherein the thermal radiation member further includes the adhesion layer, the pad layer and the thermal radiation member are attached through the adhesive layer and the adhesion layer overlaps the second region in the vertical direction.
Kwon discloses the thermal radiation structure 140 further includes an adhesive layer 141 (Fig. 1I). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have adhesive layer between the chip and the thermal radiation in order to attach the thermal radiation to the chip.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ko et al., U.S. Publication No. 2022/0020701, in view of Kim, U.S. Patent No. 9,978,731.
Regarding claim 17, Ko fails to disclose the connection structure includes a PCB substrate. Kim discloses the semiconductor package including a connection structure wherein the connection structure includes a PCB substrate (Col. 8). It would have been obvious to one having ordinary skill in the art at the time the invention was made to use PCB substrate in order to obtain a better thermal radiation, improve electrical connection, and to support or protect the chip.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ko et al., U.S. Publication No. 2022/0020701, in view of Hwang, U.S. 2023/0105942.
Regarding claim 18, Ko fails to disclose the connection includes a lower connection dielectric layer, a connection molding layer on the lower connection dielectric layer, an upper connection dielectric layer on the connection molding layer, and a through connector that penetrates the upper connection dielectric layer and the connection molding layer. Hwang discloses the connection includes a lower connection dielectric layer 310, a connection molding layer 310/320 on the lower connection dielectric layer (the layer where 122 embedded, Fig. 8), an upper connection dielectric layer on the connection molding layer 310/320, and a through connector that penetrates the upper connection dielectric layer 510 and the connection molding layer 310/320 [0017]. It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply Hwang’s in Ko’s device in order to improve electrical connectivity.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
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/THAO P LE/Primary Examiner, Art Unit 2818