DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I (claims 1-14) and Species I (claims 1-2 and 4-14) in the reply filed on 02/09/2026 is acknowledged. Thus, claims 1-2 and 4-14 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-2 and 4-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is not clear because it recites the limitation "a respective subset of the dielectric material layers" (emphasis added) in lines 9-10. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “a respective subset of the dielectric material layers” (as recited in lines 9-10) is:
“the respective dielectric material layer” (emphasis added).
It should be noted that: Applicant should consistently use the same language for the same element in the claim.
Claim 4 is not clear because it recites the limitation "a respective subset of the electrically conductive layers" (emphasis added) in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “a respective subset of the electrically conductive layers” (as recited in line 2) is:
"the respective electrically conductive layer" (emphasis added).
Claim 6 is not clear because it recites the limitation "each of the dielectric material layers" (emphasis added) in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “each of the dielectric material layers” (as recited in line 1) is:
“the respective dielectric material layer” (emphasis added).
Claim 8 is not clear because it recites the limitation "interfaces between a respective insulating layer and a respective electrically conductive layer in the composite layers" (emphasis added) in lines 2-4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “interfaces between a respective insulating layer and a respective electrically conductive layer in the composite layers” (as recited in lines 2-4) is:
“interfaces between the respective dielectric material layer and the respective electrically conductive layer in the composite layers” (emphasis added).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 4-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TSUTSUMI et al. (U.S 2022/0157841 A1).
As to claim 1, TSUTSUMI et al. disclose in Figs. 13A & 15A a device structure, comprising: an alternating stack (comprising layers 132, 146, 170, 180, 232, 246) of insulating layers (170, 180) and composite layers (comprising layers 132, 146, 232, 246) located over a source layer (9) (Fig. 13A, para. [0083]-[0084], [0089], [0093], [0156], [0160], [0184]), wherein each of the composite layers (comprising 132, 146, 232, 246) includes a combination of a respective dielectric material layer (132, 232) and a respective electrically conductive layer (146, 246) (Fig. 13A, para. [0103]-[0104], [0156], [0160]); memory openings (comprising 49, 149, 249, Figs. 4, 7A, 8 & 9A) vertically extending through the alternating stack (comprising 132, 146, 170, 180, 232, 246) (Figs. 4, 7A, 8, 9D, 9F & 13A, para. [0100]-[0101], [0113], [0115]); memory opening fill structures (comprising 148, 50, 60, 63, Fig. 5A, 9F, 9H) located in the memory openings (comprising 49, 149, 249, Figs. 4, 7A, 8 & 9A) (Figs. 5A, 7A, 8, 9A, 10A, para. [0101], [0117]), wherein each of the memory opening fill structures (comprising 148, 50, 60, 63, Fig. 5A, 9F, 9H) comprises a respective vertical stack of memory elements (comprising 52, 54, 56) and a respective vertical semiconductor channel (“semiconductor channel layers” 601, 602) (Figs. 9H, 10A, para. [0133]-[0134]); and contact via structures (comprising 86, 88) vertically extending through the respective dielectric material layer (132, 232) and the insulating layers (170, 180) in the alternating stack (comprising 132, 146, 170, 180, 232, 246) and contacting a horizontal surface of a respective one of the electrically conductive layers (146, 246) in the alternating stack (comprising 132, 146, 170, 180, 232, 246) (Fig. 15A, para. [0168], [0169]).
As to claim 4, as applied to claim 1 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: via-fill pillar structures (20, Fig. 10A) vertically extending through the respective electrically conductive layer (146, 246), having top surfaces within a first horizontal plane, and having bottom surfaces at different vertical distances from the first horizontal plane (Fig. 10A, para. [0141]-[0142]).
As to claim 5, as applied to claims 1 and 4 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the limitation: wherein: the contact via structures (comprising 86, 88) are arranged along a first horizontal direction with a uniform pitch (Fig. 15A); the via-fill pillar structures (20, Fig. 10A) are arranged along the first horizontal direction with the uniform pitch and are laterally offset from the contact via structures (86, 88) along a second horizontal direction perpendicular to the first horizontal direction; and each of the contact via structures (comprising 86, 88) is laterally offset from a respective one of the via-fill pillar structures (20) by a lateral offset distance (Fig. 15A).
As to claim 6, as applied to claims 1 and 4 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the limitation: wherein the respective dielectric material layer (132, 232) comprises a sidewall segment that is equidistant from a periphery of a respective one of the via-fill pillar structures (20) (Fig. 15A).
As to claim 7, as applied to claims 1, 4 and 5 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: lateral isolation trenches (“drain-select-level dielectric isolation structures” 72, para. [0111]) vertically extending through each of the composite layers (comprising 132, 146, 232, 246) within the alternating stack (comprising 132, 146, 170, 180, 232, 246) and laterally extending along a first horizontal direction (Figs. 15A, 16A, para. [0111]-[0112]); and lateral isolation trench fill structures (the lateral isolation trench fill structures include “a dielectric material such as silicon oxide” of 72, para. [0111], [0161]) located in a respective one of the lateral isolation trenches (“drain-select-level dielectric isolation structures” 72, para. [0111]) (Fig. 15A), wherein each of the lateral isolation trench fill structures (the lateral isolation trench fill structures include “a dielectric material such as silicon oxide” of 72, para. [0111]) and the via-fill pillar structures (20) comprises a same set of at least one fill material (“dielectric core” 62, Fig. 9H) that includes an insulating fill material (“dielectric core”, para. [0140]) (Fig. 9H, para. [0140]).
As to claim 8, as applied to claims 1, 4, 5 and 7 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: support wall structures (comprising 76, 270 & 280, Fig. 16A) in contact with a respective subset of the lateral isolation trench fill structures (the lateral isolation trench fill structures include “a dielectric material such as silicon oxide” of 72, para. [0111]) and in contact with interfaces between the respective dielectric material layer (132, 232) and the respective electrically conductive layer (146, 246) in the composite layers (comprising layers 132, 146, 232, 246) and vertically extending through each layer within the alternating stack (comprising layers 132, 146, 170, 180, 232, 246) (Fig. 16A).
As to claim 9, as applied to claim 1 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: memory-side dielectric material layers (comprising 282, 284, Fig. 16) overlying the alternating stack (comprising layers 132, 146, 170, 180, 232, 246) (Fig. 16A, para. [0165], [0170]); and memory-side metal interconnect structures (98 and 96, Fig. 16A) including bit lines (“bit lines” 98) and memory-side bonding pads (“upper metal line structures” 96) embedded within the memory-side dielectric material layers (comprising 282, 284, Fig. 16) (Fig. 16A, para. [0170]).
As to claim 10, as applied to claims 1 and 9 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: a first logic die (700, Fig. 17A) comprising first logic-side bonding pads (798) electrically bonded to the memory-side bonding pads (998) (Figs. 17A, 18A, para. [0173], [0176], [0180]).
As to claim 11, as applied to claims 1, 9 and 10 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: backside dielectric material layers (see dielectric material layers in die 700, Fig. 18A) located underneath the source layer (9, Fig. 18A) and embedding backside metal interconnect structures (comprising “pads” 798, and all additional pads in die 700, Fig. 18A) and backside bonding pads (798) (Fig. 18A, para. [0176]-[0179]), wherein a first subset of the backside metal interconnect structures (comprising “pads” 798, and all additional pads in die 700, Fig. 18A) is electrically connected to a respective one of the contact via structures (88, 188, Fig. 18A) and a second subset of the backside metal interconnect structures (comprising all metal interconnects/pads in die 900, Fig. 18A) is electrically connected to the source layer (9) (Fig. 18A, para. [0176]-[0179], [0181]).
As to claim 12, as applied to claims 1, 9, 10 and 11 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: a second logic die (900) comprising second logic-side bonding pads (998) electrically bonded to the backside bonding pads (798) (Fig. 18A, para. [0177]-[0179]).
As to claim 13, as applied to claims 1, 9, 10, 11 and 12 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the limitation: wherein: the first logic die comprises a bit line driver circuit (630) which is electrically connected to the bit lines (Figs. 17A-17B, para. [0174]); and the second logic die (900) comprises a word line driver circuit (620) which is electrically connected to the electrically conductive layers (146, 246) through the contact via structures (88, 188, Fig. 18A) (Figs. 17A-17B, 18A, para. [0174]).
As to claim 14, as applied to claims 1, 9 and 10 above, TSUTSUMI et al. disclose in Figs. 13A & 15A all claimed limitations including the device structure further comprising: wherein the first logic die (700) comprises a bit line driver circuit (630) which is electrically connected to the bit lines, and a word line driver circuit (620) which is electrically connected to the electrically conductive layers (146, 246) through the contact via structures (88, 188, Fig. 18A) (Figs. 17A-17B, 18A, para. [0174]).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: TSUTSUMI et al. (U.S 2022/0157842 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/Primary Examiner, Art Unit 2817 May 25, 2026
Prosecution Insights