DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I (claims 1-12) in the reply filed on 03/06/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, and 7-12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SAID et al. (U.S 2024/0105623 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As to claim 1, SAID et al. disclose in Figs. 13B-13D & 19D a memory device, comprising:
an alternating stack (132, 232; 146, 246) of insulating layers (132, 232) and electrically conductive layers (146, 246) (Fig. 19D, para. [0211], [0215]);
a memory opening (149/49, para. [0166], [0172], [0163], [0165], [0196]) vertically extending through the alternating stack (132, 232; 146, 246) (Fig. 4A, para. [0166], [0172], [0163], [0165], [0196]);
a memory opening fill structure (“memory stack structure” 55, Fig. 13B) located in the memory opening (149/49) and comprising a memory film (50) (Fig. 13B, para. [0195]-[0197]) and
a vertical semiconductor channel (60/60L) comprising a first semiconductor material (such as “amorphous silicon or polysilicon”, para. [0191]) (Fig. 13B, para. [0191], [0196]); and
a source structure (“source-level material layers” 110, Fig. 13D) comprising an interfacial source layer (comprising layers 114, 116, 117 & 118, Fig. 13D) and a primary source layer (“lower source-level material layer” 112, Fig. 13D), wherein the interfacial source layer (comprising layers 114, 116, 117 & 118, Fig. 13D) comprises a second semiconductor material (at least layer 114 of interfacial source layer can be made of “a silicon-germanium alloy”, para. [0205]) that has a different band gap from a band gap of the first semiconductor material (the material of “vertical semiconductor channel” 60/60L can be made by “amorphous silicon or polysilicon”, para. [0191]) and is in contact with an end portion of the vertical semiconductor channel (60/60L) (Figs 13D & 14, para. [0205], [0191]), and the primary source layer (“lower source-level material layer” 112) comprises a third semiconductor material (“doped polysilicon or doped amorphous silicon”, para. [0142]) that has a different band gap from the band gap of the second semiconductor material (at least layer 114 of interfacial source layer can be made of “a silicon-germanium alloy”, para. [0205]), and the primary source layer (112, Fig. 13D) is in contact with the interfacial source layer (comprising layers 114, 116, 117 & 118, Fig. 13D) (see Fig. 13E).
It should be noted that: the interfacial source layer (at least “source contact layer” 114 of interfacial source layer, Fig. 13D) comprises a second semiconductor material that has a different band gap from a band gap of the first semiconductor material (of channel 60/60L) because they are made by different materials (see above rejection); and the primary source layer (112) comprises a third semiconductor material that has a different band gap from the band gap of the second semiconductor material (material of at least layer 114 of interfacial source layer: “a silicon-germanium alloy”, para. [0205]) because they are made by different materials (see above rejection).
As to claim 2, as applied to claim 1 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein the primary source layer (112, 13D) comprises a horizontally-extending portion located over a most proximal insulating layer (bottom layer 132) of the insulating layers (132, 232) of the alternating stack (132, 232; 146, 246) (Fig. 19D).
As to claim 3, as applied to claims 1 and 2 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein the horizontally-extending portion of the primary source layer (112) is vertically spaced from the most proximal insulating layer (bottom layer 132) by a horizontally-extending portion of the interfacial source layer (comprising layers 114, 116, 117 & 118, Fig. 13D) that contacts a horizonal surface of the most proximal insulating layer (bottom layer 132) (see Fig. 13D).
As to claim 7, as applied to claim 1 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein the interfacial source layer (comprising layers 114, 116, 117 & 118, Fig. 13D) is in contact with a cylindrical surface segment of an inner sidewall of the vertical semiconductor channel (60/60L) (Fig. 13D).
As to claim 8, as applied to claims 1 and 7 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein the interfacial source layer (comprising layers 114, 116, 117 & 118, Fig. 13D) is also in contact with an annular end surface of the vertical semiconductor channel (60/60L) (Fig. 13D).
As to claim 9, as applied to claim 1 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein: the first semiconductor material (material of 60/60L can be “amorphous silicon or polysilicon” that has 1.5-1.7 eV, para. [0191]) has a first band gap (1.5-1.7 eV); the second semiconductor material (material of at least layer 114: silicon germanium having about 0.67 – 1.1 eV, para. [0205]) has a second band gap (0.67 – 1.1 eV); the third semiconductor material (material of 112: “doped semiconductor material” having 1.12 eV, para. [0142]) has a third band gap (1.12ev); and the second band gap (about 0.67 – 1.1 eV) is narrower than the first band gap (1.5-1.7eV) and narrower than the third band gap (1.12 eV) (Fig. 13D, para. [0205], [0142]).
As to claim 10, as applied to claim 1 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein: the first semiconductor material (of 60/60L) comprises a first doped silicon material having a doping of a first conductivity type, para. [0131], [0193]) (Figs. 9C, 13D, para. [0131], [0193]); the second semiconductor material comprises a silicon germanium material (“second semiconductor material” includes at least layer 114 which may be made of: “silicon-germanium alloy”, para. [0205]) (Fig. 13D, para. [0205]); and the third semiconductor material (material of 112, para. [0142]) comprises a second doped silicon material having a doping of a second conductivity type opposite to the first conductivity type (Fig. 13D, para. [0142], [0193]).
As to claim 11, as applied to claim 1 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein the memory opening fill structure (“memory stack structure” 55, Fig. 13B) further comprises: a dielectric core (62, Fig. 9C-9D) that is laterally surrounded by the vertical semiconductor channel (60/60L) (Figs. 9c_9D, para. [0192]-[0193]); and a drain region (63) in contact with another end portion of the vertical semiconductor channel (60/60L) and is vertically spaced from the source structure (“source-level material layers” 110, Fig. 13D) by the dielectric core (62) (Fig. 9D & 13D, para. [0194]).
As to claim 12, as applied to claim 1 above, SAID et al. disclose in Figs. 13B-13D & 19D all claimed limitations including the limitation: wherein: the interfacial source layer (comprising layers 114, 116, 117 & 118, Fig. 13D) contacts an end portion of an inner cylindrical sidewall of the memory film (50) and a horizontal surface of the vertical semiconductor channel (60/60L) (Fig. 13D, para. [0190], [0195]-[0196]); and the primary source layer (112) is not in direct contact with the memory film (50) (Fig. 13C).
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 May 30, 2026
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