Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 14 – 18 have been withdrawn/cancelled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group 1, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/22/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 19 is rejected under 35 U.S.C. 102a (1) as being anticipated by Chang et al. (US 2020/0006470, hereinafter Chang).
With respect to claim 19, Chang discloses a method (Para 0020), comprising:
forming a stack (Fig. 5B) having a peripheral portion and a middle portion (the stack has a peripheral and middle portion), the forming of the stack including:
forming a first electrode (20’) on a first conductive layer (10 – Para 0019); forming a first dielectric layer (22’) on the first electrode; forming a second electrode (24’) on the first dielectric layer; and forming a second conductive layer (28’ – Para 0067) on the second electrode (Fig. 5B);
removing the second conductive layer, the second electrode, and a portion of the first dielectric layer in the peripheral portion of the stack such that a sidewall of the middle portion of the stack is exposed (Fig. 5D); and forming a second dielectric layer (30) on the first dielectric layer and on the sidewall of the middle portion of the stack (Fig. 5G).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 - 22 and 24 - 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Summerfelt et al. (US 2003/0129771, hereinafter Summerfelt).
With respect to claim 20, Chang does not explicitly disclose
wherein an upper surface of the second dielectric layer is recessed compared to an upper surface of the second conductive layer, and sidewalls of the first electrode, the first dielectric layer, and the second dielectric layer are aligned with each other.
In an analogous art, Summerfelt discloses wherein an upper surface of the second dielectric layer is recessed compared to an upper surface of the second conductive layer (Fig. 20), and sidewalls of the first electrode, the first dielectric layer, and the second dielectric layer are aligned with each other (Fig. 18 & 20). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Summerfelt’s disclosure in order to expose the structure to perform further processing.
With respect to claim 21, Chang discloses a method (Para 0020), comprising:
forming a first electrode (20’ of Fig. 5B) on a first conductive layer (10 – Para 0019);
forming a first dielectric layer (22’) on the first electrode; forming a second electrode (24’) on the first dielectric layer; forming a second conductive layer (28’-Para 0067) on the second electrode;
forming sidewalls of the second conductive layer, the second electrode, and the first dielectric layer and an upper surface of the first dielectric layer by removing portions of the second conductive layer, the second electrode, and the first dielectric layer (Fig. 5D); forming a second dielectric layer (30 of Fig. 5G) on the sidewalls of the second conductive layer, the second electrode, and the first dielectric layer and the upper surface of the first dielectric layer (Fig. 5G).
Chang does not explicitly disclose exposing an upper surface of the second conductive layer by removing a portion of the second dielectric layer.
In an analogous art, Summerfelt discloses exposing an upper surface of the second conductive layer (306) by removing a portion of the second dielectric layer (300 – Para 0138).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Summerfelt’s disclosure in order to expose the structure to perform further processing.
With respect to claim 22, Chang/Summerfelt discloses the method of claim 22.
Chang does not explicitly disclose wherein removing the portion of the second dielectric layer includes forming an upper surface of the second dielectric layer that is lower than the upper surface of the second conductive layer.
In an analogous art, Summerfelt discloses wherein removing the portion of the second dielectric layer includes forming an upper surface of the second dielectric layer (300 of Fig. 20) that is lower than the upper surface of the second conductive layer (306).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Summerfelt’s disclosure in order to expose the structure to perform further processing.
With respect to claim 24, Chang discloses wherein the first and second dielectric layers include silicon nitride (Para 0022; 0027; layers 22 and 30 comprises of SiN).
With respect to claim 25, Chang does not explicitly disclose wherein the first and second electrodes include tantalum nitride.
In an analogous art, Summerfelt discloses wherein the first and second electrodes include tantalum nitride (Para 0048 – gate electrode can comprise of TaN).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang’s method by having Summerfelt’s disclosure in order to improve the performance of the device by improving thermal stability.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chang/Summerfelt in view of Chang et al. (US 2023/0326890, hereinafter Chang).
With respect to claim 23, Chang discloses wherein the second conductive layer include aluminum (Para 0067).
Chang does not explicitly disclose that the first conductive layer includes aluminum.
In an analogous art, Chang discloses that the first conductive layer includes aluminum (Para 0048).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Chang/Summerfelt’s method by having Chang’s disclosure in order to improve the performance of the device by providing high electron velocity and thermal stability.
Allowable Subject Matter
Claims 1-13 have been allowed.
With respect to claim 1, none of the prior art on record disclose or render obvious the claimed limitations including “etching away, by localized etching from the upper face of the stack, the second conductive layer, the second electrode, and a part of the first dielectric layer in a peripheral part of the stack; forming a second dielectric layer over the whole surface of the stack on the upper face of the stack; and etching away, by non-localized vertical anisotropic etching, the second dielectric layer, the first dielectric layer, and the first electrode until exposing an upper face of the second conductive layer in a middle part of the stack and an upper face of the first conductive layer in the peripheral part of the stack” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Claims 2-13 have been allowed by virtue of dependency on claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899