DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/03/2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claims 1-10 objected to because of the following informalities:
Claim 1, line 1: “electronic device” should read “An electronic device”
Claims 2-5, respective line 1’s: “Electronic device” should read “The electronic device”
Claim 6, line 1: “method of manufacturing” should read “A method of manufacturing…”
Claims 7-10, respective line 1’s: “Method” should read “The method”
Claim 6, lines 1-2: “the provision of a support substrate” should read “providing a support substrate”
Claim 6, lines 2-3: “the forming of a layer made of …” should read “forming a layer made of…”
Claim 7, lines 1-2: “forming of said layer” should read “forming the layer”
Claim 8, lines 1-2: “the epitaxial growth of single-crystal SiC” should read --- epitaxially growing single crystal SiC ---
Claim 9, line 3: “a layer attached to said support substrate” should read --- “the layer attached to said support substrate”
Claim 10, lines 1-2: “the epitaxial growth of single-crystal SiC” should read --- epitaxially growing single crystal SiC ---
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishiguchi (U.S. PG Pub No US2018/0233562A1).
Regarding claim 1, Nishiguchi teaches an electronic device (100) fig. 2 [0143] comprising a stack of a support substrate (10) fig. 2 [0143] made of single-crystal SiC (silicon carbide [0143]) having a first surface (12) fig. 2 [0144] and a layer (20) fig. 2 [0145] made of single-crystal SiC (20 being single crystal epitaxial layer [0145]) comprising a second (bottom of 20) surface opposite (opposing) the first surface (12), wherein the first surface (12) corresponds to an (0001) plane (“surface 12 may correspond to a [0001] plane” [0144]) of the SiC single crystal [0144] of the support substrate (10) and the second surface (bottom of 20) corresponds to a plane inclined by at least 1° [0143] with respect to an (0001) plane [0144] in the (11-20) direction (off angle in 0001 direction [0144] could be in 11-20 direction [0144, 0104]) of the SiC single crystal of the layer (101 of 20) (20 is epitaxially formed with and therefore adopts orientation of first main surface 11 [0144, 0147]; first main surface 11 and epitaxial layer grown thereon may be angled off relative to (0001) plane [0147] in “not more than 10°” [0144], hence, could be equal to 10° in a direction [0144] such as (11-20) direction [0104]).
Regarding claim 6, Nishiguchi teaches a method of manufacturing [see fig. 6, 0063] an electronic device (100) fig. 2 [0143] comprising providing of a support substrate (10) fig. 2 [0143] made of single-crystal SiC (silicon carbide [0143]) having a first surface (12) fig. 2 [0144],
forming a layer (20) fig. 2 [0145] made of single-crystal SiC (20 being single crystal epitaxial layer [0145]) attached to the support substrate (10), the layer (20) comprising a second (bottom) surface opposite (opposing) the first surface (12), wherein the first surface (12) corresponds to an (0001) plane (“surface 12 may correspond to a [0001] plane” [0144]) of the SiC single crystal [0144] of the support substrate (10) and the second surface (bottom of 20) corresponds to a plane inclined by at least 1° [0143] with respect to an (0001) plane [0144] in the (11-20) direction (off angle in 0001 direction [0144] could be in 11-20 direction [0144, 0104]) of the SiC single crystal of the layer (101 of 20) (20 is epitaxially formed with and therefore adopts orientation of first main surface 11 [0144, 0147]; first main surface 11 and epitaxial layer grown thereon may be angled off relative to (0001) plane [0147] in “not more than 10°” [0144], hence, could be equal to 10° in a direction [0144] such as (11-20) direction [0104]).
Regarding claim 7, Nishiguchi teaches the method of manufacturing [see fig. 6, 0063] according to claim 6. Nishiguchi also teaches comprising forming the layer (20) fig. 2 [0145] from a substrate (10) fig. 2 [0144] made of single-crystal SiC [0144].
Regarding claim 8, Nishiguchi teaches the method of manufacturing [see fig. 6, 0063] according to claim 7. Nishiguchi also teaches comprising epitaxially growing [0145] single-crystal SiC (20) fig. 2 [0145] on said substrate (10) fig. 2 [0144].
Regarding claim 9, Nishiguchi teaches the method of manufacturing [see fig. 6, 0063] according to claim 7. Nishiguchi also teaches comprising the forming of a fragilized area (BPD surrounding-area relatively-fragilized [0151-0153]) in the substrate (10) fig. 2 [0143] along a plane (BPD plane indicated in fig. 2) and the separation of the substrate (10) along said plane into two portions (to above/below BPD plane), one (portion above 10) of which corresponds to the layer (20 material) fig. 1 [0053] attached to said support substrate (10).
Regarding claim 10, Nishiguchi teaches the method of manufacturing [see fig. 6, 0063] according to claim 6. Nishiguchi also teaches comprising the epitaxial growth (of 102) fig. 2 [0087] (see fig. 6, step S04 [0084]) of single-crystal SiC [0145] on said layer (101 of 20 [0087-0088]; initial single crystal layer 101 of 20 may be expanded by epitaxial growth of second layer 102 [0088] such that 101 and 102 of 20 are “indistinguishable” parts of same crystal [0088]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kato (U.S. PG Pub No US2019/0219628A1) in view of Nishiguchi (U.S. PG Pub No US2018/0233562A1).
Regarding claim 1, Kato teaches an electronic device (50) fig. 2 [0031] comprising a stack (50 comprising 50a-50b) of a support substrate (50a) fig. 2 [0031] made of SiC [0031] having a first (top of 50a) surface and of a layer made of SiC (50b) fig. 2 [0031] (epitaxial film 50b) comprising a second (bottom of 50b) surface (directly) opposite the first surface (top of 50a), wherein the first surface (top of 50a) corresponds to an (0001) plane (“face” [0031]) of the SiC crystal [0031] of the support substrate (50a) and the second surface (bottom of 50b) corresponds to a plane inclined [0031] (by some angle) with respect to an (0001) plane [0031] ([0031] teaches that 50a has (0001) face with top of 50a corresponding to that (0001) face [0031] while 50b may be formed at a predetermined off angle with respect to the 0001 face of 50a [0031]).
However, Kato does not explicitly disclose the substrate (50a) is made of single crystal SiC (crystallinity of SiC layer 50a not specified [0031]), the layer (50b) is made of single-crystal SiC (crystallinity of SiC layer 50b not specified [0031]), and the second surface (bottom of 50b) corresponds to a plane inclined by at least 1° with respect to an (0001) plane in (11-20) direction of the SiC single crystal of the layer (50b) (specific off angle direction and angle-degree not specified [0031]).
Nishiguchi teaches an electronic device (100) fig. 2 [0101] wherein the substrate (10) fig. 2 [0103] made of single crystal SiC [0103], the layer (20) fig. 2 [0104] is made of single-crystal SiC [0104], and the second surface (bottom of 20) corresponds to a plane inclined by at least 1° with respect to an (0001) plane in the (11-20) direction [0104-0106] of the SiC single crystal of the layer (20) (epitaxial single crystal SiC layer 20 [0106] grown to match the orientation of underlying surface 11 of 10 [0104-0106]; both surface 11 and 20 may have off angle “not less than 1° and not more than 8° relative to a (0001) plane” and “ the off angle is provided is desirably the <11-20> direction” [0104]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the SiC support substrate and epitaxial layer of Kato to be explicitly formed of single crystal SiC [0104, 0106] and with the off-angle characteristics specified by [0104] of Kato in order to ensure high quality silicon carbide layers [0104-0106] with well-controlled orientations [0104] to improve the manufacturing costs [0103] and reliability [0107-0108] of the semiconductor device(s) formed therefrom, as taught by Nishiguchi.
Regarding claim 4, Kato in view of Nishiguchi teaches the electronic device (50) fig. 2 [0031] according to claim 1. Kato also teaches wherein the second surface (bottom of 50b) fig. 2 [0031] is in mechanical contact with the first surface (top of 50a) fig. 2 [0031].
Regarding claim 5, Kato in view of Nishiguchi teaches the electronic device (50) fig. 2 [0031] according to claim 1. Kato also teaches comprising at least one electronic component (50c of 50b) fig. 2 [0031] (50c may host semiconductor element such as MOS-FET) [0031] formed at least by treatment [0031] of the layer (50b).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Nishiguchi (U.S. PG Pub No US2018/0233562A1), as applied in claim 1 above, in view of Fukuda (U.S. PG Pub No US2020/0083330A1) (of record).
Regarding claim 2, Nishiguchi teaches the electronic device (100) fig. 2 [0143] as discussed in claim 1 above. However, Nishiguchi does not explicitly disclose wherein the support substrate (10) fig. 2 [0143] has a density of extended defects greater than 1,000 basal plane dislocation BPD defects/cm2 (density of BPD’s not explicitly disclosed).
Fukada teaches an electronic device (10) fig. 1 [0004] wherein the support substrate (1) fig. 1 [0053] has a density of extended defects greater than 1000 basal plane dislocation (BPD) defects/cm2 [0012, 0087, 0107] (the SiC support substrate 1 can have basal plane dislocations as high as 5000 BPD defects/cm2).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the support substrate of Nishiguchi to be a low-cost substrate having a density of BPD dislocations as high as 5000 BPD / cm^2 [0107] in order to reduce device manufacturing costs [0107] without compromising the quality of the epitaxial layer grown thereon [0107], as taught by Fukuda.
Regarding claim 3, Nishiguchi teaches the electronic device (100) fig. 2 [0143] as discussed in claim 1 above. However, Nishiguchi does not explicitly disclose wherein the layer (20) fig. 2 [0145] has a density of defects smaller than 250 BPD defects/cm2 (density of BPD’s not explicitly disclosed).
Fukada teaches an electronic device (10) fig. 1 [0004] wherein the layer (2) fig. 1 [0055] has a density of defects smaller than 250 BPD defects/cm2 [0107] (the SiC layer 2 can have basal plane dislocations of 0.1 BPD defects/cm2 or less).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the epitaxial layer of Nishiguchi to have a low concentration of BPD dislocations such as basal plane dislocations of 0.1 BPD defects/cm2 or less [0107] in order to increase the quality of the device formed from the epitaxial layer [0135-0136], as taught by Fukuda.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
13. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nishiguchi (U.S. PG Pub No US2018/0233562A1) (of record) explicitly teaches the epitaxial growth of SiC on the surface of a SiC single-crystal substrate resulting in a layer of epitaxially grown single-crystal silicon carbide [0104-0106]. Suzuki (U.S. PG Pub No US2017/0204531A1) (of record) explicitly teaches an offset angle θ=0° and describes a treatment used to produce a SiC_PN diode involving a SiC layer and substrate. Newly-added Seki (U.S. PG Pub No US2017/0067183A1) teaches another example of epitaxial growth of SiC in an off angle from (0001) orientation in the (11-20) direction.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/12/2026
Prosecution Insights