DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is responsive to the amendment and election received November 06, 2025. Claims 15-20 are canceled. Claims 21-26 are added. Claims 1-14 and 21-26 are pending in the application.
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1-14 and 21-26 in the reply filed on November 06, 2025 is acknowledged.
Applicant has canceled all claims not directed to the elected Species I, therefore no claims are withdrawn from consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 25, 2023 is being considered by the examiner.
Drawings
The drawings were received on July 25, 2023. These drawings are acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 14, 21, 22, 24, and 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Doany et al. (US Patent 9,285,554, hereinafter referred to as “Doany”). Doany anticipates claims:
1. An integrated chip (photonic chip 100 is interpreted as the integrated chip), comprising:
a semiconductor substrate (silicon substrate layer 110 is interpreted as the semiconductor substrate);
a photonic device (the fiber array connector with turning mirror and lens, see figure 2, unlabeled, and waveguide 114, are together interpreted as the photonic device) arranged over and spaced from the semiconductor substrate (see figure 2);
a lower optical routing structure (the grating 130 is interpreted as the lower optical routing structure) arranged below and spaced from the semiconductor substrate (see figure 2); and
a micro-lens (see figure 2, the lens shown integrated into 110 is interpreted as the micro-lens) underlying the semiconductor substrate (see figure 2, it’s underlying the top surface of the semiconductor substrate and is therefore interpreted as underlying the substrate) and elevated relative to the lower optical routing structure (see figure 2), wherein the micro-lens has an upper surface defined by semiconductor material of the semiconductor substrate (see figure 2; all surfaces of the micro-lens are defined by semiconductor material of the substrate).
2. The integrated chip according to claim 1, wherein the upper surface of the micro-lens is elevated relative to a bottommost surface of the semiconductor substrate (see figure 2).
3. The integrated chip according to claim 1, wherein the lower optical routing structure comprises a grating structure, which underlies the micro-lens (see figure 2).
4. The integrated chip according to claim 1, further comprising:
a heater device (the ceramic package 140 is interpreted as the heater device – the resistance of the electrical pathways of the package can generate heat and are interpreted as the heater device) underlying the lower optical routing structure (see figure 2).
5. The integrated chip according to claim 1, further comprising: an upper optical routing structure (114) arranged over and spaced from the semiconductor substrate; wherein the upper and lower optical routing structures are optically coupled together by an optical path defined in part by the semiconductor material of the semiconductor substrate (see figure 2).
6. The integrated chip according to claim 5, wherein the upper optical routing structure and the photonic device are level with each other (see figure 2).
7. The integrated chip according to claim 1, wherein the semiconductor substrate completely separates the upper and lower optical routing structures from each other (see figure 2).
8. An integrated chip (photonic chip 100 is interpreted as the integrated chip), comprising:
a semiconductor substrate (silicon substrate layer 110 is interpreted as the semiconductor substrate);
a first optical routing structure (see figure 2, the lens unlabeled but shown in the fiber array connector is interpreted as the first optical routing structure) overlying and spaced from the semiconductor substrate (see figure 2);
a second optical routing structure (grating 130 is interpreted as the second optical routing structures) underlying and spaced from the semiconductor substrate (see figure 2);
a first reflector (the turning mirror, unlabeled but shown in the fiber array connector, is interpreted as the first reflector, see figure 1 for a clear labeling of another structure substantially similar as a turning mirror) overlying the first optical routing structure; and
a second reflector (mirror 136 is interpreted as the second reflector) underlying the second optical routing structure.
9. The integrated chip according to claim 8, wherein the first and second optical routing structures are optically coupled together by a portion of the semiconductor substrate (see figure 2).
14. The integrated chip according to claim 8, wherein the first optical routing structure is semiconductive, and wherein the second optical routing structure is dielectric (see column 6, lines 12-27).
21. An integrated chip (photonic chip 100 is interpreted as the integrated chip), comprising: a semiconductor substrate (silicon substrate layer 110 is interpreted as the semiconductor substrate);
a photonic device (waveguide 114 is interpreted as the photonic device) overlying and spaced from the semiconductor substrate (see figure 2);
a semiconductor optical routing structure (the fiber array connector with turning mirror and lens are interpreted as the semiconductor optical routing structure, see column 6, lines 12-27) overlying and spaced from the semiconductor substrate, wherein the semiconductor optical routing structure is level with the photonic device (see figure 2); and
a dielectric optical routing structure (grating 130 is interpreted as the dielectric optical routing structure) underlying and spaced from the semiconductor substrate and optically coupled to the semiconductor optical routing structure through the semiconductor substrate (see figure 2).
22. The integrated chip according to claim 21, wherein the semiconductor substrate has a curved surface that separates the dielectric optical routing structure from the semiconductor optical routing structure (see figure 2).
24. The integrated chip according to claim 21, further comprising: a heater (the ceramic package 140 is interpreted as the heater– the resistance of the electrical pathways of the package can generate heat and are interpreted as the heater) underlying and spaced from the dielectric optical routing structure.
25. The integrated chip according to claim 21, further comprising: a dielectric layer between and contacting the semiconductor substrate and the photonic device and between and contacting the semiconductor substrate and the semiconductor optical routing structure (see figure 2, the air is interpreted as the dielectric layer).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10-13, 23, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Doany.
With respect to claims 10 and 11, Doany discloses the limitations of claim 8 as previously stated. Doany is silent to the limitations: wherein the first and second optical routing structures respectively comprise a first grating structure and a second grating structure, wherein the first reflector overlies the first grating structure, and wherein the second reflector underlies the second grating structure (claim 10); and wherein the first and second grating structures are directly between the first and second reflectors (claim 11).
Doany discloses various embodiments that utilize different structures for reflecting, turning and redirecting optical signals. In the embodiment shown in figure 1, Doany discloses coupling light between waveguides 102 and optical fibers 114 utilizing a grating 130, with a metal mirror 136 outside the grating, and lenses 132 and a turning mirror 120. Figure 2 shows another orientation of similar structures. Figures 3-11 show various options for layouts and combinations of different optical turning structures, arrays of the same structures, turning mirrors, lenses and numerous options for using the known reflecting and redirecting structures.
Based on all the options disclosed by Doany for routing optical signals between different optical signal carrying structures, like between integrated waveguides and fibers, or different layers of waveguides, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Doany such that the first and second optical routing structures respectively comprise a first grating structure and a second grating structure, wherein the first reflector overlies the first grating structure, and wherein the second reflector underlies the second grating structure and wherein the first and second grating structures are directly between the first and second reflectors, as Doany clearly discloses such structures function and are acceptable for performing optical coupling into or out of different waveguide structures.
With respect to claims 12 and 13, Doany discloses the limitations of claim 8 as previously stated. Doany is silent to the stack of wires and vias overlying the semiconductor substrate; a photonic device overlying and spaced from the semiconductor substrate, wherein the stack of wires and vias overlies and is electrically coupled to the photonic device, and wherein the first optical routing structure is level with the photonic device.
Doany further discloses the inclusion of a photonic device (photonics chip 110, see figure 2). Further, the examiner takes official notice that stacks of wires and vias overlying semiconductor substrates and a photonic device overlying and spaced from the semiconductor substrate, wherein the stack of wires and vias overlies and is electrically coupled to the photonic device, and wherein the first optical routing structure is level with the photonic device, are all well-known in the optical communications arts, and are beneficially utilized to run electrical and optical signals between different layers and components required in integrated circuits. Thusly, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Doany such that the stack of wires and vias overlying the semiconductor substrate; a photonic device overlying and spaced from the semiconductor substrate, wherein the stack of wires and vias overlies and is electrically coupled to the photonic device, and wherein the first optical routing structure is level with the photonic device, as claimed, because these structures and layouts are beneficially utilized to run electrical and optical signals between different layers and components required in integrated circuits.
With respect to claim 23, Doany discloses the limitations of claim 21 as previously stated. Doany is silent to wherein the semiconductor optical routing structure comprises silicon and the dielectric optical routing structure comprises silicon nitride. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the semiconductor optical routing structure comprises silicon and the dielectric optical routing structure comprises silicon nitride, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
With respect to claim 26, Doany discloses the limitations of claim 21 as previously stated. Doany further discloses that the structures disclosed therein include methods of fabricating including, among other things, anti-reflective coatings (see column 4, lines 59-67). However, Doany is silent to an anti-reflective layer between the semiconductor substrate and the dielectric optical routing structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include an anti-reflective layer between the semiconductor substrate and the dielectric optical routing structure to reduce unwanted reflections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M BEDTELYON whose telephone number is (571)270-1290. The examiner can normally be reached 8:00am - 4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/John Bedtelyon/Primary Examiner, Art Unit 2874