DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 12/19/2025 that has been entered, wherein claims 1-6 and 8 are pending and claim 7 is canceled.
Specification
The objection to the specification is withdrawn in light of Applicant’s amendment of 12/19/2025.
Claim Rejections - 35 USC § 112
The rejection of claims 1-8 under 35 USC 112(b) is withdrawn in light of Applicant’s amendment of 12/19/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Horie et al. (US 2007/0045798 A1) in view of Hung et al. (US 2020/0219786 A1), Lin et al. (US 2024/0071974 A1) and Akiba et al. (US 2020/0006303 A1) as cited in the IDS of 7/25/2023 all of record.
Regarding claim 1, Horie teaches a semiconductor device(Fig. 2) comprising:
a wiring substrate(11, ¶0032) having an upper surface, a lower surface opposite the upper surface, and a core insulating layer(insulating material of 11, ¶0032) located between the upper surface and the lower surface;
a semiconductor chip(12, ¶0033) having a first surface, a plurality of protruding electrodes(12A, ¶0033), and a second surface opposite the first surface, the semiconductor chip(12, ¶0033) being mounted on the wiring substrate(11, ¶0032) via the plurality of protruding electrodes(12A, ¶0033, please see section 4) such that the first surface faces the upper surface of the wiring substrate(11, ¶0032);
a plurality of balls(18, ¶0041) formed on the lower surface of the wiring substrate(11, ¶0032); and
a heat sink(141, ¶0059) having a first portion(141a, ¶0051) fixed to the second surface of the semiconductor chip(12, ¶0033) via a first adhesive layer(16, ¶0040), and a second portion(141c, ¶0051) located around the first portion(141a, ¶0051) and fixed to the wiring substrate(11, ¶0032) via a second adhesive layer(17, ¶0040),
wherein a thickness of the first portion(141a, ¶0051) of the heat sink(141, ¶0059) and a thickness of the second portion(141c, ¶0051) of the heat sink(141, ¶0059) are the same as each other(Fig. 2),
wherein, in transparent plan view, a portion of the plurality of balls(18, ¶0041) is arranged at a position overlapping with each of the second portion(141c, ¶0051) of the heat sink(141, ¶0059) and the second adhesive layer(17, ¶0040),
wherein the first adhesive layer(16, ¶0040) and the second adhesive layer(17, ¶0040) include a same kind of material as each other(¶0070), and
wherein when a shortest distance from a contacting surface of the first adhesive with the first portion(141a, ¶0051) of the heat sink(141, ¶0059) to a contacting surface of the first adhesive with the second surface of the semiconductor chip(12, ¶0033) is assumed to a first thickness(thickness of resin adhesive layer, ¶0055), and when a shortest distance from a contacting surface of the second adhesive with the second portion(141c, ¶0051) of the heat sink(141, ¶0059) to a contacting surface of the second adhesive with the upper surface of the wiring substrate(11, ¶0032) is assumed to a second thickness(T, ¶0055), the second thickness(T, ¶0055) is greater(¶0057) than the first thickness(thickness of resin adhesive layer, ¶0055).
Horie does not explicitly state the plurality of balls(18, ¶0041) is a plurality of solder balls. Horie does teaches the plurality of balls(18, ¶0041) are metal balls(¶0041) and similar metal balls 12A comprise solder balls(¶0034). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use solder balls, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. MPEP 2144.07
Horie is not relied on to teach a thickness of the first portion(141a, ¶0051) fixed to the second surface of the semiconductor chip(12, ¶0033) via the first adhesive layer(16, ¶0040) is greater than both a thickness of the core insulating layer(insulating material of 11, ¶0032) of the wiring substrate(11, ¶0032) and a thickness of the semiconductor chip(12, ¶0033), the first adhesive layer(16, ¶0040) and the second adhesive layer(17, ¶0040) include a same kind of filler as each other, the second thickness(T, ¶0055) is greater(¶0057) than two times the first thickness(thickness of resin adhesive layer, ¶0055).
Hung teaches a semiconductor device(Fig. 4) wherein the second thickness(T1, ¶0027) is greater than two times(¶0027, please see table below for T1/T2 for ranges disclosed by Hung) the first thickness(T2, ¶0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horie, so that the second thickness is greater than two times the first thickness, as taught by Hung, in order to have reduced thicknesses, improved thermal performance, improved reliability, and reduced defects(¶0030).
T1 um
T2 um
T1/T2
100
30
3
100
200
1
100
60
2
200
60
3
200
30
7
200
150
1
300
150
2
300
60
5
Horie and Hung are not relied on to teach a thickness of the first portion(141a, ¶0051) fixed to the second surface of the semiconductor chip(12, ¶0033) via the first adhesive layer(16, ¶0040) is greater than both a thickness of the core insulating layer(insulating material of 11, ¶0032) of the wiring substrate(11, ¶0032) and a thickness of the semiconductor chip(12, ¶0033), the first adhesive layer(16, ¶0040) and the second adhesive layer(17, ¶0040) include a same kind of filler as each other.
Lin teaches a semiconductor device(Fig. 1) wherein the thickness of the first portion(46, ¶0021) fixed to the second surface of the semiconductor chip(10, 12, ¶0017) via the first adhesive layer(48, ¶0021) is greater(Fig. 1) than a thickness of the core insulating layer(30, ¶0019) of the wiring substrate(14, ¶0019), the first adhesive layer(48, ¶0021) and the second adhesive layer(47, ¶0021) include a same kind of filler as each other(¶0021). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horie, so that a thickness of the first portion fixed to the second surface of the semiconductor chip via the first adhesive layer is greater than a thickness of the core insulating layer of the wiring substrate and the first adhesive layer and the second adhesive layer include a same kind of filler as each other, as taught by Li, in order to further promote the heat spreading and/or heatsinking performance of the heat sink(¶0021).
Horie, Hung and Lin are not relied on to teach a thickness of the first portion(141a, ¶0051) is greater than a thickness of the semiconductor chip(12, ¶0033).
Akiba teaches a semiconductor device(Fig. 7) wherein the thickness of the first portion(4a) of the heat sink(LD, ¶0096) is greater(¶0096) than a thickness of the semiconductor chip(CHP1, ¶0096). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horie, so that the thickness of the first portion of the heat sink is greater than a thickness of the semiconductor chip, as taught by Akiba, in order to discharge heat generated in the semiconductor chip to the outside(¶0184).
Regarding claim 2, Horie teaches the semiconductor device according to claim 1, wherein the second thickness(T, ¶0055) is less than or equal to a shortest distance(h, ¶0053) from the first portion(141a, ¶0051) of the heat sink(141, ¶0059) to the upper surface of the wiring substrate(11, ¶0032).
Regarding claim 3, Horie teaches the semiconductor device according to claim 1, wherein the heat sink(141, ¶0059) having:
a first lower surface facing the second surface of the semiconductor chip(12, ¶0033) via the first adhesive layer(16, ¶0040); and
a second lower surface facing the upper surface of the wiring substrate(11, ¶0032) via the second adhesive layer(17, ¶0040), and
wherein a shortest distance(T) from the second lower surface of the heat sink(141, ¶0059) to the upper surface of the wiring substrate(11, ¶0032) is less than a shortest distance(h) from the first lower surface of the heat sink(141, ¶0059) to the upper surface of the wiring substrate(11, ¶0032).
Regarding claim 4, Horie teaches the semiconductor device according to claim 3, but is not relied on to teaches the second thickness(T, ¶0055) is less than or equal to five times the first thickness(thickness of resin adhesive layer, ¶0055).
Hung teaches a semiconductor device(Fig. 4) wherein the second thickness(T1, ¶0027) is less than or equal to five times(¶0027, please see table above for T1/T2 for ranges disclosed by Hung) the first thickness(T2, ¶0027). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horie, so that the second thickness is less than or equal to five times the first thickness, as taught by Hung, in order to have reduced thicknesses, improved thermal performance, improved reliability, and reduced defects(¶0030).
Regarding claim 5, Horie teaches the semiconductor device according to claim 1, but is not relied on to teaches each of the first adhesive layer(16, ¶0040) and the second adhesive layer(17, ¶0040) includes an aluminum filler.
Lin teaches a semiconductor device(Fig. 1) wherein each of the first adhesive layer(48, ¶0021) and the second adhesive layer(47, ¶0021) include includes an aluminum filler(¶0021). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horie, so that each of the first adhesive layer and the second adhesive layer include includes an aluminum filler, as taught by Li, in order to further promote the heat spreading and/or heatsinking performance of the heat sink(¶0021).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Horie et al. (US 2007/0045798 A1), Hung et al. (US 2020/0219786 A1), Lin et al. (US 2024/0071974 A1) and Akiba et al. (US 2020/0006303 A1) as cited in the IDS of 7/25/2023 as applied to claim 1 above, further in view of Arrington et al. (US 2021/0202348 A1), all of record.
Regarding claim 6, Horie, in view of Hung, Lin and Akiba, teaches the semiconductor device according to claim 1, but is not relied on to teach a storage modulus of each of the first adhesive layer(16, ¶0040) and the second adhesive layer(17, ¶0040) is greater than 0, and less than or equal to 200 MPa.
Arrington teaches a semiconductor device(Fig. 9) wherein a storage modulus of the first adhesive layer(540, ¶0035) is greater than 0, and less than or equal to 200 MPa(¶0035). Using the adhesive layer of Arrington in the device of Horie would result in a storage modulus of each of the first adhesive layer and the second adhesive layer is greater than 0, and less than or equal to 200 MPa. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horie, so that a storage modulus of each of the first adhesive layer and the second adhesive layer is greater than 0, and less than or equal to 200 MPa, as taught by Arrington, so that that little stress is transferred to an underlying underfill fillet and/or wiring substrate so as to not damage the underlying material(¶0035).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Horie et al. (US 2007/0045798 A1), Hung et al. (US 2020/0219786 A1), Lin et al. (US 2024/0071974 A1) and Akiba et al. (US 2020/0006303 A1) as cited in the IDS of 7/25/2023, as applied to claim 1 above, further in view of Okada et al. (US 2014/0159224 A1) all of record.
Regarding claim 8, Horie, in view of Hung, Lin and Akiba, teaches the semiconductor device according to claim 1, but are not relied on to teach in plan view, the wiring substrate(11, ¶0032) is comprised of a quadrangular shape, and wherein, in plan view, a length of each of four sides of the wiring substrate(11, ¶0032) is greater than or equal to 20 mm.
Okada teaches an semiconductor device(Fig. 1B) wherein in plan view, the wiring substrate(SUB, ¶0045) is comprised of a quadrangular shape(¶0033), and wherein, in plan view, a length of each of four sides of the wiring substrate(SUB, ¶0045) is greater than or equal to 20 mm(¶0045). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Horie, so that in plan view, the wiring substrate is comprised of a quadrangular shape, and wherein, in plan view, a length of each of four sides of the wiring substrate is greater than or equal to 20 mm, as taught by Okada, in order to shorted the offset distance from the center point of the substrate to the center point of the largest semiconductor device resulting in effective device warpage reduction(¶0075).
Response to Arguments
Applicant's arguments filed 12/19/2025 have been fully considered but they are not persuasive.
Regarding claim 1, Applicant’s argue nothing in the cited portions of Lin describes the thickness comparison between the lid 46 (allegedly corresponding to the claimed first portion) and the core 30 (allegedly corresponding to the claimed core insulating layer). In fact, nowhere in Lin describes the thicknesses of the lid 46 and the core 30. The Office appears to rely solely on Lin's FIG. 1. Applicant directs attention to § 2125 of the MPEP. For example, drawings and pictures can anticipate claims if they clearly show the structure that is claimed, and only where the drawings are to scale or dimensions are otherwise described (see MPEP § 2125, citing In re Mraz, 455 F.2d 1069 (CCPA 1972)). That is, the Office must first determine whether the drawings are to scale, and if the dimensions are described (see MPEP § 2125). When the cited art does not disclose that the drawings are to scale and is silent as to dimensions, arguments based on measurement of the drawing features are of little value (see Hockerson-Halberstadt, Inc. v. Avia Group Int'l, 222 F.3d 951, 956 (Fed. Cir. 2000) (The disclosure gave no indication that the drawings were drawn to scale. "[I]t is well established that patent drawings do not define the precise proportions of the elements and may not be relied on to show particular sizes if the specification is completely silent on the issue.")). As noted above, Lin is completely silent as to the dimensions of the lid 46 and the core 30, and does not disclose that the drawings are to scale. Accordingly, Lin cannot be relied upon to disclose or suggest the claimed thickness relationship between the first portion and the core insulating layer of the wiring substrate.
The examiner respectfully submit that the MPEP 2125 states “the description of the article pictured can be relied on, in combination with the drawings, for what they would reasonably teach one of ordinary skill in the art”. A person of ordinary kill in the art viewing Fig. 1 of Lin, would observe that the lid 46 is depicted thicker than the core 30. Without needing precise measurements, a person of ordinary skill in the art would reasonably be motivated to make “the thickness of the first portion(46, ¶0021) fixed to the second surface of the semiconductor chip(10, 12, ¶0017) via the first adhesive layer(48, ¶0021) is greater(Fig. 1) than a thickness of the core insulating layer(30, ¶0019)” in order to further promote the heat spreading and/or heatsinking performance of the heat sink(¶0021).
Applicants further argue nothing in the cited portions of Akiba describes the thickness comparison between the heat radiating portion 4a of the lid LD (allegedly corresponding to the claimed first portion) and the semiconductor chip CHP1 (allegedly corresponding to the claimed semiconductor chip). The Office appears to rely solely on Akiba's FIG. 7. Similar to the improper reliance of Lin's drawings, Applicant submits that Akiba is also completely silent as to the dimensions of the heat radiating portion 4a of the lid LD and the semiconductorchipCHP1,and does not disclose that the drawings are to scale. Accordingly, according to § 2125 of the MPEP, Akiba cannot be relied upon to disclose or suggest the claimed thickness relationship between the first portion and the semiconductor chip.
The examiner respectfully submits that in addition to figure 7 of Akiba's depicting the lid LD to be thicker than the semiconductor chip CHP1, the cited ¶0096 states “wiring substrate SUB1 and the lid LD have substantially the same size and are larger than the size of the semiconductor chip CHP1”. Without needing precise measurements, a person of ordinary skill in the art would reasonably be motivated to make “the thickness of the first portion(4a) of the heat sink(LD, ¶0096) is greater(¶0096) than a thickness of the semiconductor chip(CHP1, ¶0096)” in order to discharge heat generated in the semiconductor chip to the outside(¶0184).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892