Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species I, A, ii in the reply filed on 3/20/2026 is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/30/2026. Applicant did not specify which claims read on the elected species, examiner has determined that of the elected claims, claims 1-6 and 9-10 read on the elected Species claim 7 requires “the second electrode is further disposed between the semiconductor layer and the second dielectric layer” however this only reads on the embodiments of species C as shown in Figs. 11 and 29 as described in paragraph [0227] and not with respect to the elected species. Claim 8 describes “a fourth dielectric layer disposed between the first electrode and the semiconductor layer” This is only described with respect to Species G as shown in Figs. 13 and 22 and describes in paragraph [0230] and not with respect to the elected species
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 10 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Kameshiro (US 20080285325 A1 hereinafter Kameshiro).
Regarding claim 1, Kameshiro teaches in Figs. 18B with associated text a thin-film transistor (TFT) comprising: a gate 5 comprising: a top portion (see annotated Fig. below); a gate base (see annotated Fig. below) disposed at the top portion; a bottom portion (see annotated Fig. below); and a gate body (see annotated Fig. below) extending from the gate base to the bottom portion and comprising a side surface (see annotated Fig. below [0131]); a semiconductor layer 3 disposed along the side surface (Fig. 18B, [0131]); a first electrode 1 disposed at the bottom portion and electrically coupled to the semiconductor layer (Fig. 18B, [0131]); a second electrode 2 disposed between the first electrode and the gate base and electrically coupled to the semiconductor layer (Fig. 18B, [0131]); a first dielectric layer 12 disposed between the second electrode and the first electrode separating the second electrode from the first electrode (Fig. 18B, [0137]); and a second dielectric layer 4 separating the semiconductor layer from the gate (Fig. 18B, [0138]).
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Regarding claim 2, Kameshiro teaches the second electrode is disposed proximate to the gate base (Fig. 18B).
Regarding claim 3, Kameshiro teaches the gate base comprises a surface, and wherein the semiconductor layer comprises an extension portion (see annotated Fig. above) extending along the surface.
Regarding claim 4, Kameshiro teaches the semiconductor layer comprises an extension portion disposed between the gate body and the first electrode (see annotated Fig. above).
Regarding claim 5, Kameshiro teaches the semiconductor layer surrounds the side surface (Fig. 18B, [0138]).
Regarding claim 6, Kameshiro teaches the semiconductor layer comprises a side located away from the second dielectric layer, and wherein the second electrode is further disposed on the side (Fig. 18B).
Regarding claim 10, Kameshiro teaches the first electrode is a drain of the thin-film transistor, and wherein the second electrode is a source of the thin-film transistor [0137].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kameshiro as applied to claim 1 and further in view of Ratnam et. Al. (US 20180197988 A1 hereinafter Ratnam).
Regarding claim 9, Kameshiro teaches the thin-film transistor of claim 1.
Kameshiro does not specify a modulation gate electrode disposed between the first electrode and the second electrode and surrounded by the first dielectric layer.
Ratnam discloses in Figs. 40A with associated text a thin-film transistor similar to that of Kameshiro comprising a modulation gate electrode 152 ([0242]) disposed between a first electrode 10 and a second electrode 280 (Fig. 40A-40B, [0244]-[0245]) and surrounded by a first dielectric layer (502, 122 and 158) (Fig. 40A, [0248]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a modulation gate similar to that of Ratnam in the method of Kameshiro because according to Ratnam the voltages of the three or four gate electrodes can be controlled to provide full depletion in both of the vertical semiconductor channel strips 30 during operation of the vertical field effect transistor, thereby enhancing the current-voltage characteristics of the vertical field effect transistor. Specifically, the on-current of the vertical field effect transistor of the present disclosure can be greater than the on-current of a comparative exemplary vertical field effect transistor having the same channel length (along the direction of the current flow) and the same channel width (i.e., the total interface area with the gate dielectrics) and operating at the same operating voltage due to the complete control of the channel through full depletion, further, the three or four gate electrodes of the vertical field effect transistors of the present disclosure in conjunction with the thin vertical semiconductor channel strips 30 that enables full depletion can provide a lesser off-current than the off-current of a comparative exemplary vertical field effect transistor having the same channel length and the same channel width and operating at the same operating voltage due to the complete control of the channel through full depletion [0259].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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