DETAILED ACTION
This Action is responsive to the communication filed on 07/28/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Suzuki (US 2014/0175508).
Regarding claim 1, Suzuki (see, e.g., FIG. 5) discloses a semiconductor device comprising:
a first electrode 10 (Para 0034);
a first semiconductor region 22 of a first conductivity type e.g., n-type disposed above the first electrode 10 (Para 0035);
an insulating film 44 disposed in the first semiconductor region 22 (Para 0043);
a second electrode 42 disposed in the insulating film 44 (Para 0043);
a second semiconductor region 23 of a second conductivity type e.g., p-type adjacent to the second electrode 42 via the insulating film 44 (Para 0035, Para 0038);
a third semiconductor region 24 of the first conductivity type e.g., n-type disposed on the second semiconductor region 23 (Para 0035); and
a third electrode 30 electrically coupled to a contact portion 32 (left), the contact portion 32 (left) being in contact with the first semiconductor region 22 to form a Schottky junction on a first side surface e.g., right side surface of 32 (left), being in contact e.g., indirect contact with the second semiconductor region 23 and the third semiconductor region 24 on a second side surface e.g., left side of 32 (left) opposite to the first side surface e.g., right side of 32 (left), and having a bottom surface e.g., bottom surface of 32 (left) located above a bottom surface e.g., bottom surface of 23 of the second semiconductor region 23 (Para 0033, Para 0041, Para 0042).
Regarding claim 2, Suzuki (see, e.g., FIG. 5) teaches the semiconductor device according to claim 1, wherein the first semiconductor region 22 has a protrusion 26 (middle) having a third side surface e.g., left side surface of 26 (middle) in contact with the first side surface e.g., right side surface of 32 (left) of the contact portion 32 (left), and the protrusion 26 (middle) is in contact with another contact portion 32 (right) to form a Schottky junction on a fourth side surface e.g., right side surface of 26 (middle) opposite to the third side surface e.g., left side surface of 26 (middle).
Regarding claim 3, Suzuki (see, e.g., FIG. 5) teaches the semiconductor device according to claim 1, wherein the contact portion 32 (left) is in contact with the first semiconductor region 22 in an entire region of the first side surface e.g., right side surface of 32 (left) to form a Schottky junction.
Regarding claim 7, Suzuki (see, e.g., FIG. 5) teaches the semiconductor device according to claim 1, wherein the first semiconductor region 22, the second semiconductor region 23, and the third semiconductor region 24 are made of silicon including impurities (Para 0035-Para 0039).
Regarding claim 8, Suzuki (see, e.g., FIG. 5) teaches the semiconductor device according to claim 7, wherein the contact portion 32 (left) includes titanium, cobalt, nickel, platinum, or tungsten (Para 0041, Para 0042).
Regarding claim 10, Suzuki (see, e.g., FIG. 5) teaches the semiconductor device according to claim 1, wherein the first conductivity type e.g., n-type is n-type, and the second conductivity type e.g., p-type is p-type.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2014/0175508), in view of Saito (US 2012/0056262).
Regarding claim 4, although Suzuki shows substantial features of the claimed invention, Suzuki fails to expressly teach the semiconductor device according to claim 1, further comprising: a fourth semiconductor region of the second conductivity type that is in contact with the contact portion and the second semiconductor region and has a higher impurity concentration than the second semiconductor region.
Saito (see, e.g., FIG. 1), on the other hand, teaches a fourth semiconductor region 14 of the second conductivity type e.g., p-type that is in contact e.g., direct contact / indirect contact with the contact portion e.g., downward protruding portion of 33 (in direct contact) and the second semiconductor region 12 (in indirect contact) and has a higher impurity concentration than the second semiconductor region 12 for the purpose of moderating the electric field strength applied to the Schottky junction (Para 0022, Para 0028, Para 0029, Para 0053).
Examiner note: Examiner notes that p+ denotes a heavy or high level of doping. In this case, the fourth semiconductor region 14 is p+-type and the second semiconductor region 12 is p-type.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the fourth semiconductor region as described by Saito to the contact portion of Suzuki for the purpose of moderating the electric field strength applied to the Schottky junction (Para 0053).
Regarding claim 5, Saito (see, e.g., FIG. 1) teaches the semiconductor device according to claim 4, wherein the fourth semiconductor region 14 is disposed between a bottom surface of the contact portion e.g., bottom surface of the downward protruding portion of 33 and the first semiconductor region 11.
Regarding claim 6, although Suzuki shows substantial features of the claimed invention, Suzuki fails to expressly teach the semiconductor device according to claim 1, further comprising: a fourth electrode disposed below the second electrode in the first insulating film and electrically coupled to the third electrode.
Saito (see, e.g., FIG. 1), on the other hand, teaches a fourth electrode 31 disposed below the second electrode 32 in the first insulating film 41, 42, 43 and electrically coupled to the third electrode 33 for the purpose of reducing the gate-to-drain capacitance, thereby realizing high speed switching (Para 0024, Para 0026, Para 0035, Para 0055).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the fourth electrode as described by Saito to the device of Suzuki for the purpose of reducing the gate-to-drain capacitance, thereby realizing high speed switching (Para 0055).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (US 2014/0175508), in view of Shimizu (US 2017/0077299).
Regarding claim 9, although Suzuki shows substantial features of the claimed invention, Suzuki fails to expressly teach the semiconductor device according to claim 1, wherein the insulating film is made of silicon oxide or silicon nitride.
Shimizu (see, e.g., FIG. 5), on the other hand, teaches the insulating film 16 is made of silicon oxide or silicon nitride for the purpose of utilizing a material that is applicable, i.e., suitable, to being utilized as a gate insulating film (Para 0037).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the insulating film of Suzuki to be made of silicon oxide or silicon nitride as described by Shimizu for the purpose of utilizing a material that is applicable, i.e., suitable, to being utilized as a gate insulating film (Para 0037).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
