Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/25/2023 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitations of claim 8 are unclear in view of the limitations of claim 7, which claim 8 depends on, and the specification/drawings. Claim 8 recites the limitation “a first plurality of bit lines . . .each bit line of the first plurality of bit lines extends in the first direction . . . a second plurality of bit lines . . . each bit line of the second plurality of bit lines extends in the first direction”. However, claim 8 depends on claim 7 which recites “electrical isolation structure has a planar shape that extends in a first direction from the top to the bottom of each 3D block of the first plurality of 3D blocks and that extends in a second direction across each of the 3D blocks in the first plurality of 3D blocks”. Figure 4C and [0086] shows that “The planar shape of the electrical isolation structures 408 extends in the z-direction from the top to the bottom of each block” i.e. the first direction is the z-direction. Figure 5A and [0086] shows that “planar shape of the electrical isolation structures 408 extends in the y-direction across each of the blocks in the plane”, i.e. the second direction is the y-direction. Finally, [0072] states that “Each plane has a number of bit lines 415, with each bit line extending the in the y-direction”, i.e. it is understood by the examiner that the bit lines are extending in the second (y) direction, not the first (z) direction. Therefore, claim 8 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention. For the purpose of this examination, claim 8 will be interpreted as “a first plurality of bit lines . . .each bit line of the first plurality of bit lines extends in the second direction . . . a second plurality of bit lines . . . each bit line of the second plurality of bit lines extends in the second direction”.
The limitations of claim 14 are unclear in view of the limitations of claim 12, which claim 14 depends on, and the drawings. Claim 14 recites the limitation “etching a second trench between the first plane and the dummy array region . . . forming the second electrical isolation structure in the second trench”. However, claim 14 depends on claim 12 which recites “forming a second electrical isolation structure between the dummy array region and the second plane”. These two limitations appear to contradict one another as it is unclear how the second trench, formed between the first plane and the dummy array, may accommodate the second electrical isolation structure formed between the dummy array and the second plane. Therefore, claim 14 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor, or a joint inventor, regards as the invention. Figures 4A and 4C of the instant application shows the second electrical isolation structure (#408(1)) as being located in a planar trench which is located between the second plane (#400(1)) and the dummy array region (#410-1). For this reason and for the purpose of this examination, claim 14 will be interpreted to read as “etching a second trench between the second plane and the dummy array region . . . forming the second electrical isolation structure in the second trench”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, and 12-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0033311 A1; Yang, Chin-Cheng; 02/2023; (“Yang”). An annotated version of Figure 1 from Yang is provided below and considered in the following rejections.
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Regarding Claim 1. Yang discloses An apparatus (#10, Figure 1, three-dimensional memory device where Figures 2A-2D, 3A-3J, and 4A-4B are varying views of the structure and its method of making according to [0007]-[0010]) comprising:
a first array region (#A1, Figure 1 annotated) having a first stack (#120 in #TR1, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]) and a second stack (#120 in #TR2, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]), the first array region having a first word line hookup region between the first stack and the second stack (central #SR regions, Figures 1 annotated and 3J, staircase regions between #TR1 and #TR2 where the gate/word lines are connected to by contacts #COA);
a second array region (#A2, Figure 1 annotated) having a third stack (#120 in #TR3, Figures 1 and 3J, gate stack structure interpreted to have the same structure as #TR1/#TR2 based on [0022]-[0024] indicating the stack is formed in each region) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]) and a fourth stack (#120 in #TR4, Figures 1 and 3J, gate stack structure interpreted to have the same structure as #TR1/#TR2 based on [0022]-[0024] indicating the stack is formed in each region) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]), the second array region having a second word line hookup region between the third stack and the fourth stack (central #SR regions, Figures 1 annotated and 3J, staircase regions between #TR3 and #TR4 where the gate/word lines are connected to by contacts #COA);
a dummy array region (#DAR, Figure 1 annotated) between the first array region and the second array region (Figure 1 annotated, #DAR is between #A1 and #A2), the dummy array region comprising a stack (#DGS, Figure 1 annotated, dummy gate stack structures) of alternating first layers comprising a first material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide) and second layers comprising a second material that is different from the first material (#105b, Figure 3A, [0023] and [0036], sacrificial layers formed in all of the regions, retained in the dummy region according to [0036], and made of silicon nitride);
a first electrical isolation structure (#G1 and #G2, Figure 1, groupings of slit structure #SLT2) between the dummy array region and the first array region (Figure 1 annotated, at least #SLT25 is between #DAR and #A1), wherein the first electrical isolation structure comprises an insulator between the dummy array region and the second stack ([0040], all of #SLT2, including the portion between #DAR and #TR2, is formed of a dielectric/insulating material such as silicon oxide); and
a second electrical isolation structure (#G3 and #G4, Figure 1, groupings of slit structure #SLT2) between the dummy array region and the second array region (Figure 1 annotated, at least #SLT25 of #G3 and #G4 is between #DAR and #A2), wherein the second electrical isolation structure comprises an insulator between the dummy array region and the third stack ([0040], all of #SLT2, including the portion between #DAR and #TR3, is formed of a dielectric/insulating material such as silicon oxide).
Regarding Claim 2. Yang discloses The apparatus of claim 1, wherein:
the first layers of the dummy array region are aligned with the insulating layers in the first array region and the second array region (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions respective stacks to have the same level before separation into respective arrays);
the second layers of the dummy array region are aligned with the conductive layers in the first array region and the second array region (#105b, Figure 3A, [0023] and [0036], sacrificial layers formed in all of the regions respective stacks to have the same level before separation into respective arrays, retained in the dummy region according to [0036], where the #105b layers are replaced with the gate layers #GL in Figures 3G-3I such that they are aligned); and
the insulating layers are formed from the first material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide).
Regarding Claim 3. Yang discloses The apparatus of claim 2, wherein the second material is an insulator material (#105b, Figure 3A, [0023] and [0036], sacrificial layers formed in all of the regions, retained in the dummy region according to [0036], and made of silicon nitride).
Regarding Claim 5. Yang discloses The apparatus of claim 1, wherein:
the first stack of alternating insulating layers and conductive layers (#120 in #TR1, Figures 1 and 3J, gate stack structure) comprises a first staircase structure in the first word line hookup region (Figure 1 annotated and Figure 3J, right #SR, staircase region, of #TR1);
the second stack of alternating insulating layers and conductive layers (#120 in #TR2, Figures 1 and 3J, gate stack structure) comprises a second staircase structure in the first word line hookup region (Figure 1 annotated and Figure 3J, left #SR, staircase region, of #TR2);
the third stack of alternating insulating layers and conductive layers (#120 in #TR3, Figures 1 and 3J, gate stack structure interpreted to have the same structure as #TR1/#TR2 based on [0022]-[0024] indicating the stack is formed in each region) comprises a third staircase structure in the second word line hookup region (Figure 1 annotated and Figure 3J, right #SR, staircase region, of #TR3); and
the fourth stack of alternating insulating layers and conductive layers (#120 in #TR4, Figures 1 and 3J, gate stack structure interpreted to have the same structure as #TR1/#TR2 based on [0022]-[0024] indicating the stack is formed in each region) comprises a fourth staircase structure in the second word line hookup region (Figure 1 annotated and Figure 3J, left #SR, staircase region, of #TR4).
Regarding Claim 6. Yang discloses The apparatus of claim 1, wherein:
the first electrical isolation structure comprises an insulator that extends from a top to a bottom of the second stack (Figure 3J, the height of the entire #SLT2 slit structure, which includes the first electrical isolation structure as described in claim 1, extends at least from a top to a bottom of the stack #120 which is formed in the region #TR2); and
the second electrical isolation structure comprises an insulator that extends from a top to a bottom of the third stack (Figure 3J, the height of the entire #SLT2 slit structure, which includes the second electrical isolation structure as described in claim 1, extends at least from a top to a bottom of the stack #120 which is formed in the region #TR3).
Regarding Claim 12. Yang discloses A method for forming adjacent planes in a memory die (#10, Figure 1, three-dimensional memory device where Figures 2A-2D, 3A-3J, and 4A-4B are varying views of the structure and its method of making according to [0007]-[0010]), the method comprising:
forming a first plane (#A1, Figure 1 annotated) having a first stack (#120 in #TR1, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]) and a second stack (#120 in #TR2, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]), the first plane having a first mid-plane word line hookup region between the first stack and the second stack (central #SR regions, Figures 1 annotated and 3J, staircase regions between #TR1 and #TR2 where the gate/word lines are connected to by contacts #COA);
forming a second plane (#A2, Figure 1 annotated) having a third stack (#120 in #TR3, Figures 1 and 3J, gate stack structure interpreted to have the same structure as #TR1/#TR2 based on [0022]-[0024] indicating the stack is formed in each region) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]) and a fourth stack (#120 in #TR4, Figures 1 and 3J, gate stack structure interpreted to have the same structure as #TR1/#TR2 based on [0022]-[0024] indicating the stack is formed in each region) of alternating insulating layers (#105a, Figure 3J, insulating material layers) and conductive layers (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]), the second plane having a second mid-plane word line hookup region between the third stack and the fourth stack (central #SR regions, Figures 1 annotated and 3J, staircase regions between #TR3 and #TR4 where the gate/word lines are connected to by contacts #COA);
forming a dummy array region (#DAR, Figure 1 annotated) between the first plane and the second plane (Figure 1 annotated, #DAR is between #A1 and #A2), including forming alternating layers of a first material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide) and a second material that is a different material than the first material (#105b, Figure 3A, [0023] and [0036], sacrificial layers formed in all of the regions, retained in the dummy region according to [0036], and made of silicon nitride);
forming a first electrical isolation structure (#G1 and #G2, Figure 1, groupings of slit structure #SLT2) between the dummy array region and the first plane (Figure 1 annotated, at least #SLT25 is between #DAR and #A1); and
forming a second electrical isolation structure (#G3 and #G4, Figure 1, groupings of slit structure #SLT2) between the dummy array region and the second plane (Figure 1 annotated, at least #SLT25 of #G3 and #G4 is between #DAR and #A2).
Regarding Claim 13. Yang discloses The method of claim 12, wherein forming the first plane, the second plane, and the dummy array region includes:
forming alternating layers of the first material and a sacrificial material that extend across the first plane, the second plane, and the dummy array region (#105a and #105b, Figure 3A, [0023] and [0036], insulating layers and sacrificial layers formed in all of the regions respective stacks to have the same level before separation into respective arrays), wherein the sacrificial material comprises the second material (#105b, Figure 3A, [0023] and [0036], sacrificial layers formed in all of the regions, retained in the dummy region according to [0036], and made of silicon nitride); and
replacing the layers of the sacrificial material in the first plane and the second plane but not the dummy array region with conductive material to form the conductive layers in the first plane and the second plane (#105b, Figure 3A, [0023] and [0036], sacrificial layers formed in all of the regions respective stacks to have the same level before separation into respective arrays, retained in the dummy region according to [0036], where the #105b layers are replaced with the gate layers #GL in Figures 3G-3I).
Regarding Claim 14. Yang discloses The method of claim 13, wherein forming the first electrical isolation structure and forming the second electrical isolation structure comprise:
etching a first trench between the first plane and the dummy array region, including etching the first trench in the alternating layers of the first material and the sacrificial material ([0033], Figures 3F to 3G, a trench #144T is formed in the alternating layers of #105a and #105b which is where the entire second slit structure #SLT2 is formed according to [0016] including the portion between #A1 and #DAR in Figure 1 annotated);
etching a second trench between the second plane and the dummy array region, including etching the first trench in the alternating layers of the first material and the sacrificial material ([0033], Figures 3F to 3G, a trench #144T is formed in the alternating layers of #105a and #105b which is where the entire second slit structure #SLT2 is formed according to [0016] including the portion between #A2 and #DAR in Figure 1 annotated);
forming the first electrical isolation structure in the first trench ([0016], Figure 1 annotated and Figure 3I to 3J, #SLT2, including the portion between #A1 and #DAR, is formed in the trench #144T); and
forming the second electrical isolation structure in the second trench ([0016], Figure 1 annotated and Figure 3I to 3J, #SLT2, including the portion between #A2 and #DAR, is formed in the trench #144T).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 7-8, 15, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0033311 A1; Yang, Chin-Cheng; 02/2023; (“Yang”) as applied to claim 1 above, and further in view of US 2019/0371811 A1; Oike, Go; 12/2019; (“Oike”).
Regarding Claim 4. Yang discloses The apparatus of claim 1, wherein:
the first array region comprises vertical [memory structures] in the first stack (#130 of #TR1 of #A1, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the first stack of the first array region);
the first array region comprises vertical [memory structures] in the second stack (#130 of #TR2 of #A1, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the second stack of the first array region);
the second array region comprises vertical [memory structures]in the third stack (#130 of #TR3 of #A2, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the third stack of the second array region);
the second array region comprises vertical [memory structures]in the fourth stack (#130 of #TR4 of #A2, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the fourth stack of the second array region); and
the dummy array region comprises dummy vertical [memory structures] (#130 of #DAR, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the dummy array region).
Yang does not explicitly disclose that the vertical memory structures in each of the first, second, third, fourth, and dummy array region are vertical NAND strings. However, Yang does teach that the memory device may be a NAND memory device in [0002].
Oike teaches a semiconductor memory device (#1, Figures 1-16, [0004]-[0018]) comprising a plurality of memory arrays (#ABLK, Figure 4, active blocks) and dummy array regions (#DBLK, Figure 4, dummy block) which are separated from one another by electrical isolation structures (#SLT, Figure 4, insulative slit according to [0115]), wherein the dummy array regions may be located between two memory arrays ([0086], “dummy block DBLK may be disposed between the active blocks ABLK arranged in the Y direction”) and both the memory arrays and the dummy arrays comprise vertical NAND strings as their respective memory structures (#MP, Figures 5, 7, and 9, [0091], “memory pillar MP functions as, for example, a single NAND string NS”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the memory pillars of Yang as vertical NAND strings, as was done in Oike, since NAND memory is known as a memory structure capable of storing memory data in a non-volatile manner (see [0032] of Oike) which has the advantage of stored data not disappearing during power-off periods of the device (see [0002] of Yang).
Regarding Claim 7. Yang discloses The apparatus of claim 1, wherein:
the first array region comprises a first plurality of 3D blocks of memory cells (#B1-#B4 of #TR1 and #TR2 in #A1, blocks of memory in each stack of the first array region), each block having a top and a bottom (Figures 1 and 3J, each block necessarily has a top and bottom in the z-direction, where each block is interpreted to have the same structure and/or height based on [0022]-[0024] indicating the stack is formed in each region);
the first electrical isolation structure has a planar shape that extends in a first direction from the top to the bottom of each 3D block of the first plurality of 3D blocks and that extends in a second direction across each of the 3D blocks in the first plurality of 3D blocks (Figure 1 and Figure 3J, each portion of #SL2 is a planar shape with a height in the z-direction extending at least from a top to a bottom of the stacks #120 and extending in a second X-direction across each of the sets of blocks #B1-#B4);
the second array region comprises a second plurality of 3D blocks of memory cells (#B1-#B4 of #TR3 and #TR4 in #A2, blocks of memory in each stack of the second array region), each block having a top and a bottom (Figures 1 and 3J, each block necessarily has a top and bottom in the z-direction, where each block is interpreted to have the same structure and/or height based on [0022]-[0024] indicating the stack is formed in each region); and
the second electrical isolation structure has a planar shape that extends in the first direction from the top to the bottom of each 3D block of the second plurality of 3D blocks and that extends in the second direction across each of the 3D blocks in the second plurality of 3D blocks (Figure 1 and Figure 3J, each portion of #SL2 is a planar shape with a height in the z-direction extending at least from a top to a bottom of the stacks #120 and extending in a second X-direction across each of the sets of blocks #B1-#B4).
Yang does not explicitly disclose that the 3D memory blocks are specifically NAND memory blocks. However, Yang does teach that the memory device may be a NAND memory device in [0002].
Oike teaches a semiconductor memory device (#1, Figures 1-16, [0004]-[0018]) comprising a plurality of memory blocks (#BLKG0-3, Figure 3, block groups) each comprising a plurality of arrays (#ABLK, Figure 4, active blocks) and dummy array regions (#DBLK, Figure 4, dummy block) which are separated from one another by electrical isolation structures (#SLT, Figure 4, insulative slit according to [0115]), wherein the dummy array regions may be located between two memory arrays ([0086], “dummy block DBLK may be disposed between the active blocks ABLK arranged in the Y direction”) and the 3D arrays are NAND memory arrays ([0032], “semiconductor memory 1 is, for example, a NAND flash memory”) with NAND strings as their respective memory structures (#MP, Figures 5, 7, and 9, [0091], “memory pillar MP functions as, for example, a single NAND string NS”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the memory arrays of Yang as NAND arrays, as was done in Oike, since NAND memory is known as a memory structure capable of storing memory data in a non-volatile manner (see [0032] of Oike) which has the advantage of stored data not disappearing during power-off periods of the device (see [0002] of Yang).
Regarding Claim 8. Yang in view of Oike disclose The apparatus of claim 7, further comprising:
a first plurality of bit lines over the first array region (Oike, [0035], “A plurality of bit lines and a plurality of word lines are provided in each of the memory cell arrays”, the bit lines are provided to connect with an associated memory cell), wherein each bit line of the first plurality of bit lines extends in the second direction (Oike, Figure 6, all of the bit lines are observed to extend in both the X and Y directions as planar structures); and
a second plurality of bit lines over the second array region (Oike, [0035], “A plurality of bit lines and a plurality of word lines are provided in each of the memory cell arrays”, the bit lines are provided to connect with an associated memory cell), wherein each bit line of the second plurality of bit lines extends in the second direction (Oike, Figure 6, all of the bit lines are observed to extend in both the X and Y directions as planar structures).
Regarding Claim 15. Yang discloses A memory device comprising:
a first plane (#A1, Figure 1 annotated) having a first stack (#120 in #TR1, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) comprising a first insulating material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide) and conductive layers comprising a conductive material (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]) and a second stack (#120 in #TR2, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) comprising the first insulating material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide) and conductive layers comprising the conductive material (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]), the first stack having a first staircase structure adjacent to the second stack (Figure 1 annotated and Figure 3J, right #SR, staircase region, of #TR1 adjacent to #TR2), the second stack having a second staircase structure adjacent to the first stack (Figure 1 annotated and Figure 3J, left #SR, staircase region, of #TR2 adjacent to #TR1);
a second plane (#A2, Figure 1 annotated) having a third stack (#120 in #TR3, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) comprising the first insulating material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide) and conductive layers comprising the conductive material (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]) and a fourth stack (#120 in #TR4, Figures 1 and 3J, gate stack structure) of alternating insulating layers (#105a, Figure 3J, insulating material layers) comprising the first insulating material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide) and conductive layers comprising the conductive material (#GL, Figure 3J, gate layers formed of a conductive material according to [0038]), the third stack having a third staircase structure adjacent to the fourth stack (Figure 1 annotated and Figure 3J, right #SR, staircase region, of #TR3 adjacent to #TR4), the fourth stack having a fourth staircase structure adjacent to the third stack (Figure 1 annotated and Figure 3J, left #SR, staircase region, of #TR4 adjacent to #TR3);
a dummy array region (#DAR, Figure 1 annotated) between the first plane and the second plane (Figure 1 annotated, #DAR is between #A1 and #A2), the dummy array region having a stack (#DGS, Figure 1 annotated, dummy gate stack structures) of alternating first layers comprising the first insulating material (#105a, Figure 3A, [0023] and [0036], insulating layers formed in all of the regions and made of silicon oxide) and second layers comprising a second insulating material (#105b, Figure 3A, [0023] and [0036], sacrificial layers formed in all of the regions, retained in the dummy region according to [0036], and made of silicon nitride);
a first slit trench fill structure (#G1 and #G2, Figure 1, groupings of slit structure #SLT2) between the dummy array region and the first plane (Figure 1 annotated, at least #SLT25 is between #DAR and #A1), wherein the first slit trench fill structure comprises an insulator between the dummy array region and the second stack ([0040], all of #SLT2, including the portion between #DAR and #TR2, is formed of a dielectric/insulating material such as silicon oxide); and
a second slit trench fill structure (#G3 and #G4, Figure 1, groupings of slit structure #SLT2) between the dummy array region and the second plane (Figure 1 annotated, at least #SLT25 of #G3 and #G4 is between #DAR and #A2), wherein the second slit trench fill structure comprises an insulator between the dummy array region and the third stack ([0040], all of #SLT2, including the portion between #DAR and #TR3, is formed of a dielectric/insulating material such as silicon oxide).
Yang does not explicitly disclose that the memory device in the considered embodiment is specifically a NAND memory device. However, Yang does teach that any memory device may be a NAND memory device in [0002].
Oike teaches a semiconductor memory device (#1, Figures 1-16, [0004]-[0018]) comprising a plurality of memory blocks (#BLKG0-3, Figure 3, block groups) each comprising a plurality of arrays (#ABLK, Figure 4, active blocks) and dummy array regions (#DBLK, Figure 4, dummy block) which are separated from one another by electrical isolation structures (#SLT, Figure 4, insulative slit according to [0115]), wherein the dummy array regions may be located between two memory arrays ([0086], “dummy block DBLK may be disposed between the active blocks ABLK arranged in the Y direction”) and the 3D arrays are NAND memory arrays ([0032], “semiconductor memory 1 is, for example, a NAND flash memory”) with NAND strings as their respective memory structures (#MP, Figures 5, 7, and 9, [0091], “memory pillar MP functions as, for example, a single NAND string NS”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the memory arrays of Yang as NAND arrays, as was done in Oike, since NAND memory is known as a memory structure capable of storing memory data in a non-volatile manner (see [0032] of Oike) which has the advantage of stored data not disappearing during power-off periods of the device (see [0002] of Yang).
Regarding Claim 17. Yang in view of Oike disclose The NAND memory device of claim 15, further comprising:
first NAND strings extending vertically through the first stack and the second stack (Yang, #130 of #TR1 and #TR2 of #A1, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the first and second stacks of the first array region which may be NAND strings as in Oike, [0091], “memory pillar MP functions as, for example, a single NAND string NS”, to form the NAND memory structures);
second NAND strings extending vertically through the third stack and the fourth stack (Yang, #130 of #TR3 and #TR4 of #A2, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the third and fourth stacks of the second array region which may be NAND strings as in Oike, [0091], “memory pillar MP functions as, for example, a single NAND string NS”, to form the NAND memory structures); and
dummy NAND strings extending vertically through the stack in the dummy array region (Yang, #130 of #DAR, Figure 1 annotated and Figure 3J, channel pillars of the memory structure located in the dummy array region which may be dummy NAND strings as in Oike, [0091], “dummy memory pillar DMP is a structural body which has the same structure as, for example, that of the memory pillar MP but is not used to store data”, to form the dummy regions of the NAND memory structures).
Regarding Claim 18. Yang in view of Oike disclose The NAND memory device of claim 15, wherein:
the first slit trench fill structure extends from a top to a bottom of the second stack (Yang, Figure 3J, the height of the entire #SLT2 slit structure, which includes the first electrical isolation structure as described in claim 1, extends at least from a top to a bottom of the stack #120 which is formed in the region #TR2); and
the second slit trench fill structure extends from a top to a bottom of the third stack (Yang, Figure 3J, the height of the entire #SLT2 slit structure, which includes the second electrical isolation structure as described in claim 1, extends at least from a top to a bottom of the stack #120 which is formed in the region #TR3).
Regarding Claim 19. Yang in view of Oike disclose The NAND memory device of claim 18, wherein:
the first plane comprises a first plurality of three-dimensional (3D) blocks of memory cells (Yang, #B1-#B4 of #TR1 and #TR2 in #A1, blocks of memory in each stack of the first array region), each 3D block having a top and a bottom (Yang, Figures 1 and 3J, each block necessarily has a top and bottom in the z-direction, where each block is interpreted to have the same structure and/or height based on [0022]-[0024] indicating the stack is formed in each region);
the first slit trench fill structure has a planar shape that extends in a first direction from the top to the bottom of each 3D block of the first plurality of 3D blocks and that extends in a second direction across each 3D block in the first plurality of 3D blocks (Yang, Figure 1 and Figure 3J, each portion of #SL2 is a planar shape with a height in the z-direction extending at least from a top to a bottom of the stacks #120 and extending in a second X-direction across each of the sets of blocks #B1-#B4);
the second plane comprises a second plurality of 3D blocks of memory cells (Yang, #B1-#B4 of #TR3 and #TR4 in #A2, blocks of memory in each stack of the second array region), each 3D block having a top and a bottom (Yang, Figures 1 and 3J, each block necessarily has a top and bottom in the z-direction, where each block is interpreted to have the same structure and/or height based on [0022]-[0024] indicating the stack is formed in each region); and
the second slit trench fill structure has a planar shape that extends that extends in the first direction from the top to the bottom of each 3D block of the second plurality of 3D blocks and that extends in the second direction across each 3D block in the second plurality of 3D blocks (Yang, Figure 1 and Figure 3J, each portion of #SL2 is a planar shape with a height in the z-direction extending at least from a top to a bottom of the stacks #120 and extending in a second X-direction across each of the sets of blocks #B1-#B4).
Regarding Claim 20. Yang in view of Oike disclose The NAND memory device of claim 19, further comprising:
a first plurality of bit lines over the first stack and the second stack (Oike, [0035], “A plurality of bit lines and a plurality of word lines are provided in each of the memory cell arrays”, the bit lines are provided to connect with an associated memory cell), wherein each bit line of the first plurality of bit lines extends in the second direction (Oike, Figure 6, all of the bit lines are observed to extend in both the X and Y directions as planar structures); and
a second plurality of bit lines over the third stack and the fourth stack (Oike, [0035], “A plurality of bit lines and a plurality of word lines are provided in each of the memory cell arrays”, the bit lines are provided to connect with an associated memory cell), wherein each bit line of the second plurality of bit lines extends in the second direction (Oike, Figure 6, all of the bit lines are observed to extend in both the X and Y directions as planar structures).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0033311 A1; Yang, Chin-Cheng; 02/2023; (“Yang”) as applied to claim 1 above, and further in view of US 2020/0203364 A1; Totoki et al.; 06/2020; (“Totoki”).
Regarding Claim 9. Yang discloses The apparatus of claim 1.
Yang does not disclose a first plurality of voltage drivers, each voltage driver in the first plurality of voltage drivers configured to provide an operating voltage to a first conductive layer in the first stack and a second conductive layer in the second stack; and a second plurality of voltage drivers, each voltage driver in the second plurality of voltage drivers configured to provide an operating voltage to a third conductive layer in the third stack and a fourth conductive layer in the fourth stack. However, Yang teaches a plurality of contacts (#COA, Figure 3J, contacts) used to deliver a provided voltage to the individual conductive layers (#GL, Figure 3J, gate layers) of the respective stacks.
Totoki teaches a semiconductor memory structure (Figure 19) comprising a plurality of conductive layers (#46, Figure 19, electrically conductive layers) in a stack with connectors (#86, Figure 19, word line contact via structures) for delivering a voltage to the conductive layers and a plurality of word line voltage drivers which are configured to provide voltage control signals to the word lines in the stack of multiple arrays ([0103], “first peripheral circuitry can include a first word line driver that drives the first electrically conductive layers 46 within the first memory die 1000 . . second peripheral circuitry can include a second word line driver that drives the second electrically conductive layers within a second memory die”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the word line voltage drivers as part of the peripheral circuitry of Totoki in the device of Yang in order to properly control/operate the word line conductive line structures of the memory arrays in the device.
Regarding Claim 10. Yang in view of Totoki discloses The apparatus of claim 9, wherein the apparatus comprises:
a first semiconductor die comprising the first array region, the second array region, the dummy array region, the first electrical isolation structure, and the second electrical isolation structure (Yang, Figures 1 annotated, 2 and 3J, the memory arrays #A1 and #A2, the dummy array region #DAR, and the isolation structures #SLT2, are all provided on the substrate #100; Totoki, Figures 14B and 19, the memory array structures #100 and isolation structures #76 separating neighboring arrays are all provided on the memory die #1000); and
a second semiconductor die bonded to the first semiconductor die, the second semiconductor die comprising the first plurality of voltage drivers and the second plurality of voltage drivers (Totoki, [0103], Figures 16 and 18, the logic die #700 is provided as a second die including all of the voltage driving structures and control circuitry).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0033311 A1; Yang, Chin-Cheng; 02/2023; (“Yang”) in view of US 2020/0203364 A1; Totoki et al.; 06/2020; (“Totoki”) as applied to claim 9 above, and further in view of US 2020/0279858 A1; Xie et al.; 09/2020; (“Xie”).
Regarding Claim 11. Yang in view of Totoki discloses The apparatus of claim 9.
Yang in view of Totoki do not disclose that the apparatus comprises a semiconductor die comprising: the first array region, the second array region, the dummy array region, the first electrical isolation structure, and the second electrical isolation structure; and the first plurality of voltage drivers and the second plurality of voltage drivers. Totoki teaches the peripheral logic circuit structure including the voltage drivers are provided on a separate logic die (#700) from the memory array structure on the memory die (#1000) as described above in the rejection of claim 10.
However, Xie teaches in [0002] and [0058] the idea of “embedding a nonvolatile memory cell and a logic semiconductor device together on the same silicon substrate”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the memory structure, including the arrays, dummy arrays, and electrical isolation structures, on the same die as the peripheral logic structure, including the voltage drivers, in the device of Yang in view of Totoki as considered by Xie since combining the structures on the same substrate (or die) “can enable improved, high-performance electronic devices, in part because the embedded memory reduces inter-chip communication” (see [0002] and [0058] of Xie).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0033311 A1; Yang, Chin-Cheng; 02/2023; (“Yang”) in view of US 2019/0371811 A1; Oike, Go; 12/2019; (“Oike”) as applied to claim 15 above, and further in view of US 2020/0203364 A1; Totoki et al.; 06/2020; (“Totoki”).
Regarding Claim 16. Yang in view of Oike discloses The NAND memory device of claim 15, further comprising:
first staircase contacts (#COA, Figures 1 and 3J, contacts in the right #SR of #TR1) that connect to respective layers of the conductive layers in the first staircase structure (Figures 1 and 3J, #COAs located in the right staircase region #SR in #TR1 and shown in Figure 3J as connecting to the gate layers #GL of the stack);
second staircase contacts (#COA, Figures 1 and 3J, contacts in the left #SR of #TR2) that connect to respective layers of the conductive layers in the second staircase structure (Figures 1 and 3J, #COAs located in the left staircase region #SR in #TR2 and shown in Figure 3J as connecting to the gate layers #GL of the stack);
third staircase contacts (#COA, Figures 1 and 3J, contacts in the right #SR of #TR3) that connect to respective layers of the conductive layers in the third staircase structure (Figures 1 and 3J, #COAs located in the right staircase region #SR in #TR3 and shown in Figure 3J as connecting to the gate layers #GL of the stack); and
fourth staircase contacts (#COA, Figures 1 and 3J, contacts in the left #SR of #TR4) that connect to respective layers of the conductive layers in the fourth staircase structure (Figures 1 and 3J, #COAs located in the left staircase region #SR in #TR4 and shown in Figure 3J as connecting to the gate layers #GL of the stack).
Yang does not disclose a first plurality of staircase voltage drivers, the first plurality of staircase voltage drivers connected to respective conductive layers in the first and second staircase structures through first and second staircase contacts; and a second plurality of staircase voltage drivers, the second plurality of staircase voltage drivers connected to respective conductive layers in the third and fourth staircase structures through third and fourth staircase contacts.
Totoki teaches a semiconductor memory structure (Figure 19) comprising a plurality of conductive layers (#46, Figure 19, electrically conductive layers) in a stack with connectors (#86, Figure 19, word line contact via structures) for delivering a voltage to the conductive layers and a plurality of word line voltage drivers which are configured to provide voltage control signals to the word lines in the stack of multiple arrays ([0103], “first peripheral circuitry can include a first word line driver that drives the first electrically conductive layers 46 within the first memory die 1000 . . second peripheral circuitry can include a second word line driver that drives the second electrically conductive layers within a second memory die”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing pluralities of word line voltage drivers as part of the peripheral circuitry of Totoki in the device of Yang in order to properly control/operate the word line conductive line structures of the memory arrays in the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2019/0043872 A1; Oh et al.; 02/2019 – Figures 5-8 show a 3D memory device comprising a plurality of memory array structures (#BLK1-2) separated from one another by a dummy array structure (#DBLK) and an insulative slit structure (#SLIT), and further including staircase contact regions (#CONT1-4) in the space between adjacent stacks (Figure 8).
US 2023/0413551 A1; Chen et al.; 12/2023 – Reference discloses a similar structure in Figures 17A and 17B including memory stacks (#232A/#246) of neighboring arrays (#UA) separated from one another by dummy array structures (#232P/#242P).
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/TYLER J WIEGAND/Examiner, Art Unit 2812