DETAILED ACTION
Election/Restrictions
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method of fabrication, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/20/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/26/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: the word “frustum” is misspelled as “frustrum” in paragraphs [0021], [0041], [0049], [0056], [0074], and [0084].
Appropriate correction is required.
Claim Objections
Claim 6 is objected to because of the following informalities: the word “frustum” is misspelled as “frustrum” in line 2.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sung et al. (US 20230329007 A1), hereinafter “Sung.”
Re: claim 1, Sung discloses an ovonic memory element (See Fig. 1; ¶0025: In the memory device, the chalcogenide material may exhibit ovonic threshold switching material characteristics), comprising:
a first electrode (Fig. 1: first electrode layer 11; ¶0050: first electrode layer 11);
a second electrode (Fig. 1: electrode 13; ¶0050: second electrode layer 13); and
an ovonic threshold switching material portion located between the first electrode and the second electrode (Fig. 1: selection layer 12; ¶0050: The selection layer 12 may include a chalcogenide material having an ovonic threshold switch (OTS) characteristic), wherein a first surface of the ovonic threshold switching material portion facing the first electrode is wider than an opposing second surface of the ovonic threshold switching material portion facing the second electrode (See Fig. 7; ¶0094: the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof).
Re: claim 2, Sung discloses the ovonic memory element of claim 1.
Sung further discloses wherein:
the first surface of the ovonic threshold switching material portion contacts the first electrode (Fig. 1: OTS layer 12 top surface contacts first electrode 11); and
the second surface of the ovonic threshold switching material portion contacts the second electrode (Fig. 1: OTS layer 12 bottom surface contacts second electrode 13).
Re: claim 3, Sung discloses the ovonic memory element of claim 2.
Sung further discloses wherein the first electrode is located above the second electrode (Fig. 1 shows a first electrode 11 which is above the second electrode 13).
Re: claim 4, Sung discloses the ovonic memory element of claim 2.
Sung further discloses wherein the first electrode is located below the second electrode (See Fig. 7; ¶0094: the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof. In other words, the orientation of the memory cell may be configured such that the first electrode, coinciding with the wider part of the memory cell, is located below the second electrode, which coincides with the thinner part of the memory cell).
Re: claim 5, Sung discloses the ovonic memory element of claim 1.
Sung further discloses wherein the ovonic threshold switching material portion comprises a chalcogenide material (¶0050: The selection layer 12 may include a chalcogenide material having an ovonic threshold switch (OTS) characteristic).
Re: claim 6, Sung discloses the ovonic memory element of claim 1.
Sung further discloses wherein the ovonic threshold switching material portion has a shape of a frustrum (¶0093: The memory cell 30 may have a pillar shape. For example, the memory cell 30 MC may have a prismatic and/or cylindrical and/or tapered shape, and may have various pillar shapes, such as a square pillar, an oval pillar, and a polygonal pillar, i.e., frustum shape).
Re: claim 7, Sung discloses the ovonic memory element of claim 6.
Sung further discloses wherein a tapered surface of the ovonic threshold switching material portion continuously extends from the first electrode to the second electrode (¶0093: The memory cell 30 may have a pillar shape. For example, the memory cell 30 MC may have a prismatic and/or cylindrical and/or tapered shape, and may have various pillar shapes, such as a square pillar, an oval pillar, and a polygonal pillar).
Re: claim 8, Sung discloses the ovonic memory element of claim 6.
Sung further discloses wherein the ovonic threshold switching material portion has a variable horizontal cross-sectional area that decreases with a vertical distance from the second electrode to the first electrode (¶0093: tapered shape; ¶0094: the memory cell 30 may have a structure in which the upper part of the memory cell 30 is wider than the lower part thereof or the lower part thereof is wider than the upper part thereof).
Re: claim 9, Sung discloses the ovonic memory element of claim 8.
Sung further discloses wherein the ovonic threshold switching material portion has a circular or oval-shaped horizontal cross-sectional shape (¶0093: …and may have various pillar shapes, such as a square pillar, an oval pillar, and a polygonal pillar).
Re: claim 10, Sung discloses the ovonic memory element of claim 8.
Sung further discloses wherein the ovonic threshold switching material portion has a rectangular horizontal cross-sectional shape (¶0093: …and may have various pillar shapes, such as a square pillar, an oval pillar, and a polygonal pillar).
Re: claim 11, Sung discloses the ovonic memory element of claim 1.
Sung further discloses wherein the ovonic threshold switching material portion is configured to store data (¶0102: The variable resistor layer 120 may store information. For example, the resistance value of the variable resistor layer 120 may vary depending on the applied voltage. The memory device 100 may store and erase digital information, such as “0” or “1”, according to a change in resistance of the variable resistor layer 120.).
Re: claim 13, Sung discloses a memory device, comprising the ovonic memory element of claim 1 (See Figs. 1 and 8);
a first electrically conductive line that laterally extends along a first horizontal direction and electrically connected to the first electrode (Fig. 8: WL is a first electrically conductive line extending along a first horizontal direction; ¶0103: The memory device 100 may have a voltage applied to the variable resistor layer 120 of the memory cell MC through the first electrode line WL, i.e., first electrically conductive line, and the second electrode line BL to allow a current to flow.);
a second electrically conductive line that laterally extends along a second horizontal direction and electrically connected to the second electrode (Fig. 8: BL is a first electrically conductive line extending along a second horizontal direction; ¶0103: The memory device 100 may have a voltage applied to the variable resistor layer 120 of the memory cell MC through the first electrode line WL and the second electrode line BL, i.e., second electrically conductive line, to allow a current to flow.); and
a metallic pillar structure located between the ovonic threshold switching material portion and one of the first or the second electrically conductive lines (Fig. 8 shows MC; ¶0100: The selection layer 110 may control a flow of current with respect to the memory device 100 electrically connected to the selection layer 110 to select the memory device 100 corresponding to the selection layer 110. For example, the selection layer 110 may include a material capable of changing resistance according to the magnitude of the voltage applied across both ends thereof. For example, the selection layer 110 may have an OTS characteristic.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. (US 20230329007 A1).
Re: claim 12, Sung discloses the ovonic memory element of claim 1.
Sung discloses an ovonic memory element comprising first and second electrodes with an ovonic threshold switching (OTS) material portion therebetween (See Fig. 1). Sung teaches that the OTS material exhibits threshold switching behavior, wherein application of set and reset pulses induces threshold voltage shifts (ΔVth) for operational functionality in memory devices (¶0082). Sung further discloses that device geometry, including tapered pillar shapes with varying cross-sections, influences structural and electrical properties such as stability and switching performance (¶0093 and ¶0109). Sung further discloses different chalcogenide material compositions which have improved endurance by suppressing or reducing a threshold voltage drift (¶0110). Sung also discloses endurance testing where threshold voltage (ΔVth) remains operable within ±15% of the initial value over many cycles, indicating recognition of relative voltage variations as a performance metric (¶0076).
Sung differs from claim 12 in that it does not expressly disclose wherein the ovonic memory element has a ΔVth/Vth value of greater than 15%. However, Sung teaches the general conditions of an OTS-based memory element with adjustable structural and compositional parameters (e.g., taper in pillar geometry, arsenic content >30 at % and up to 50 at %, and bonding configurations like Ge-S and Se-metal) that affect threshold voltage drifts.
The threshold voltage (ΔVth), and by extension the normalized ΔVth/Vth, is a result-effective variable in the art, as Sung explicitly recognizes that varying device composition and geometry modulates the magnitude of threshold voltage shifts, thereby enhancing device stability, endurance, and state distinguishability in memory applications.
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve memory performance would have routinely experiment with known fabrication variables disclosed by Sung in order to determine optimal values that increase the relative threshold voltage shift beyond the exemplified levels. Such routine optimization within the general conditions taught by Sung would have naturally led to ΔVth/Vth > 15%, as demonstrated by predictable enhancements in voltage response from tapered geometries and refined compositions (reasonable expectation of success given Sung’s teachings on parameter effects). See MPEP § 2144.05(II)(“[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Re: claim 14, Sung discloses a method of operating the ovonic memory element of claim 1 (See ¶0102 and ¶0104), comprising:
programming the ovonic threshold switching material portion to store data by applying a programming voltage between the first electrode and the second electrode (¶0104: any memory cell MC may be addressed by selecting the first electrode line WL and the second electrode line BL, and a predetermined signal may be applied between the selected first electrode line WL and the selected second electrode line BL to program the memory cell MC. In addition, by measuring the current value through the second electrode line BL, information according to the resistance value of the variable resistor layer 120 of the memory cell MC, that is, programmed information, may be read); and
reading the data stored in the ovonic threshold switching material portion by applying a read voltage between the first electrode and the second electrode (¶0104: by measuring the current value through the second electrode line BL, information according to the resistance value of the variable resistor layer 120 of the memory cell MC, that is, programmed information, may be read),
Sung differs from claim 14 in that it does not expressly disclose wherein the ovonic memory element has a ΔVth/Vth value of greater than 15%. However, Sung teaches the general conditions of an OTS-based memory element with adjustable structural and compositional parameters (e.g., taper in pillar geometry, arsenic content >30 at % and up to 50 at %, and bonding configurations like Ge-S and Se-metal) that affect threshold voltage drifts.
The threshold voltage (ΔVth), and by extension the normalized ΔVth/Vth, is a result-effective variable in the art, as Sung explicitly recognizes that varying device composition and geometry modulates the magnitude of threshold voltage shifts, thereby enhancing device stability, endurance, and state distinguishability in memory applications.
Therefore, a person having ordinary skill in the art before the effective filing date, motivated by the objective to improve memory performance would have routinely experiment with known fabrication variables disclosed by Sung in order to determine optimal values that increase the relative threshold voltage shift beyond the exemplified levels. Such routine optimization within the general conditions taught by Sung would have naturally led to ΔVth/Vth > 15%, as demonstrated by predictable enhancements in voltage response from tapered geometries and refined compositions (reasonable expectation of success given Sung’s teachings on parameter effects). See MPEP § 2144.05(II)(“Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation” (citing In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Grobis et al. (US 20200005863 A1) – See Fig. 9C
Hirayama et al. (US 20230093157 A1) – See Figs. 25-26
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898