DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/31/25 have been fully considered but they are not persuasive.
Applicant argues Okada fails to teach or suggest a recess formed within a single conductor pattern, and a recess that is integrated into a pattern and reaches its own boundary to reduce a metal-sealing interface.
In response, recesses 25a and 25b are formed in a single conductor pattern or lead 20 in Figures 2, 7, 9 of Okada. If Okada includes additional recesses not required by claim 1, the reference still meets the claim limitations
of a recess formed in the first region which includes a first pattern. Also, the terminology end and edge are often considered synonyms when referring to the boundary or limit of an area. Both can describe the point where something stops. In Figure 9 of Okada, the recess 25a “stops” at a boundary between the semiconductor element 50 and the layer 21b. Since the recess 25a is integrated in pattern 20, the second end (edge) of the first pattern reaches the fourth end (edge) of the recess as recited in claim 1. Finally, the fact that Applicant recognizes advantages which flow from the recess in the pattern, such as to reduce a metal-sealing interface, does not lend patentability to claim 1. See MPEP 2145.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4-7 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Patent Application Publication No. 2013/0343067 (Okada) in view of U.S. Patent Application Publication No. 2022/0190556 (Kigoshi).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Okada discloses (Figs. 2, 7, 9)
1. and A semiconductor device comprising:
a substrate (not shown) including a main surface ([0066]-[0069]);
a semiconductor element 50;
a connection material (not shown, [0048]);
a first bonding wire 40; and
a second bonding wire 42,
wherein the substrate (not shown) includes a conductor layer 20, 22 on the main surface,
wherein the main surface includes a first region 20a / 20b and a second region 22a / 22b that are separated from each other in a first direction in a plan view,
wherein the conductor layer 20, 22 includes a first pattern 20 in the first region 20a / 20b and a second pattern 22 in the second region 22a / 22b,
wherein the semiconductor element 50 is disposed on the first region 20a / 20b with the connection material (not shown, [0048]) interposed therebetween,
wherein one end and the other end of the first bonding wire 40 are connected to the semiconductor element 50 and the first pattern 20, respectively,
wherein one end and the other end of the second bonding wire 42 are connected to the semiconductor element 50 and the second pattern 22, respectively,
wherein a recess 25a is formed in the first region 20a / 20b,
wherein the recess 25a includes a first end (left) and a second end (below semiconductor element 50) which is opposite to the first end (left) and is closer to the second region 22a / 22b than the first end (left) in the first direction (X),
wherein the first end (left) is between the semiconductor element 50 and the other end (in contact with pad 21b) of the first bonding wire 40 in the first direction (X),
wherein the recess 25a is formed in the first pattern 20,
wherein the first pattern 20 includes a third end (left) and a fourth end (below semiconductor element 50) which is opposite to the third end (left) and is closer to the second pattern 22 than the semiconductor element 50 in the first direction (X), and
wherein the second end reaches the fourth end (both below semiconductor element 50).
Okada fails to disclose
a connection material,
Kigoshi teaches
A semiconductor device comprising:
a substrate 10 including a main surface 11;
a semiconductor element 100;
a connection material P2.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a substrate and connection material. The motivation would be they are well-known in the art as shown in Kigoshi ([0098], [0135]). See MPEP 2144.03.
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Okada discloses
2. The semiconductor device of Claim 1, wherein the recess 25a is formed in the first pattern 20, and wherein the second end is between the first end and the semiconductor element 50 in the first direction.
Okada discloses
4. (Currently Amended) The semiconductor device of Claim 1, wherein a plated film 21a / 21b is formed on a surface of the first pattern 20.
Okada discloses ([0076])
5. The semiconductor device of Claim 4, wherein the plated film 21 a / 21 b is a silver-plated film.
Okada discloses ([0051])
6. The semiconductor device of Claim 1, wherein a resin material is embedded in the recess 25a.
Okada discloses ([0044])
7. (Currently Amended) The semiconductor device of Claim 6, further comprising: a peripheral wall 10 disposed on an outer peripheral edge of the main surface to surround the semiconductor element 50 in a plan view, wherein a constituent material of the peripheral wall is the same as the resin material.
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okada in view of Kigoshi as applied to claim 7 above, and further in view of U.S. Patent Application Publication No. 2017/0092816 (Ikeda).
The combination of references fails to teach
8. The semiconductor device of Claim 7, wherein the recess extends along a second direction perpendicular to the first direction in a plan view, and wherein both ends of the recess in the second direction reach the outer peripheral edge of the main surface.
Ikeda teaches (Figs. 1-3)
A semiconductor device comprising:
wherein the recess (not labeled but below film 27 and where body 25 is filled) extends along a second direction perpendicular to the first direction in a plan view, and wherein both ends of the recess in the second direction reach the outer peripheral edge of the main surface ([0051]-[0056]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a recess that reaches the outer peripheral edge of the main surface in the modified device of Okada. The motivation would be routine engineering design considerations to contribute to an improved light outputting efficiency as taught by Ikeda ([0005], [0075]).
Okada discloses
9. The semiconductor device of Claim 8, further comprising a sealing material ([0044]) with which a space defined by the substrate (not shown) and the peripheral wall 10 is filled.
Okada discloses
10. The semiconductor device of Claim 9, wherein the semiconductor element 50 is a light-emitting element, wherein a constituent material of the sealing material is a transparent resin ([0044]), and wherein the constituent material of the peripheral wall 10 is a material that reflects light from the light-emitting element.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2010/0270571 (Seo), 20080224161 (Takada), 2017/0244014 (Park), 2017/0162485 (Yasunaga) teach a light emitting package having a recess in a conductor.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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