DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 & 7-15 are rejected under 35 U.S.C. 103 as being unpatentable over KIM (US Pub. 2021/0154794) in view of ZENG et al. (US Pub. 2022/0152742) and Kawashima (US Pub. 2004/0241963).
Regarding claim 1, KIM teaches a semiconductor device fabrication apparatus comprising:
a grinder (e.g. Section B & Section C) comprising a grinding part (e.g. Section B), the grinding part configured to grind a first surface of a substrate 11 (Fig. 2 & Fig. 3-4B);
a laser emitter (78a-78d) configured to emit a laser pulse to the first surface of the substrate 11 transferred from the grinder (Para [0056] & Fig. 2-3), while a protective tape 21 is attached to a second surface of the substrate (see Fig. 4A-4B), the second surface being opposite to the first surface 11a, the second surface including a circuit pattern thereon (note circuit patterns 19 and/or 15 in Fig. 4A-4B); and
a mount (4c or 4b) configured to receive the substrate transferred from the laser emitter (78a-78d),
wherein the grinding part is configured to grind the first surface of the substrate 11, which has been introduced into the grinder, and the laser emitter is configured to emit the laser pulse to the first surface of the substrate that has been ground (Fig. 2 and associated text).
KIM is silent on (i) wherein the laser emitter is a femtosecond pulse laser; and (ii) wherein the mount is configured to attach a die attach film to the first surface of the substrate.
ZENG teaches in Para [0014] (i) a wafer processing apparatus comprising a laser emitter that emits femtosecond laser pulse. This has the advantage of providing extremely short pulses for extremely precise scanning and imaging and/or allowing to study ultrafast molecular dynamics and create micro-scale structures while avoiding damage to surrounding areas of the semiconductor wafer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of KIM with the femtosecond laser, as taught by ZENG, so as to deliver intense energy in tiny bursts to obtain enhanced imaging/scanning while avoiding damage to surrounding areas of the semiconductor wafer.
Kawashima teaches (ii) a semiconductor device fabrication apparatus comprising a mount 20 configured to attach a die attach film 25 to a first surface of the substrate 12 (Fig. 1-Fig. 2b and associated text). This has the advantage of providing adhesion on wafer surface during die bonding operation. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of KIM and ZENG with the die attach film (DAF), as taught by Kawashima, so as to provide adhesion for a semiconductor wafer/die surface during a die bonding operation.
Regarding claim 2, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 1, wherein the grinding part comprises a first grinding part (section B), a second grinding part (section C), a polishing part (section D), the first grinding part configured to perform a first grinding process on the first surface of the substrate, the second grinding part configured to perform a second grinding process on the first surface of the substrate on which the first grinding process has been performed, and the polishing part configured to polish the first surface of the substrate on which the second grinding process has been performed, and the semiconductor device fabrication apparatus further comprises a controller 74 configured to control an operation of the polishing part (KIM’s Fig. 2 and associated text).
Regarding claim 3, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 2, wherein when the controller 74 controls the polishing part to not operate, the laser emitter is configured to emit the femtosecond pulse laser to the first surface of the substrate on which the second grinding process has been performed (KIM’s Fig. 2-3 and ZENG’s Para [0006 & 0014]).
Regarding claim 4, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 3, wherein the laser emitter is configured to remove at least a portion of the substrate by emitting the femtosecond pulse laser to the first surface of the substrate in a state in which the polishing part and the substrate are not in contact with each other (KIM’s Fig. 2-3 and ZENG’s Para [0006 & 0014]: the combination of KIM and ZENG’s device is capable of said functionality).
Regarding claim 5, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 2, wherein when the controller 74 controls the polishing part to operate, the polishing part is configured to polish the first surface of the substrate on which the second grinding process, and the laser emitter is configured to emit the femtosecond pulse laser to the first surface of the substrate that has been polished (KIM’s Fig. 2-3 and ZENG’s Para [0006 & 0014]).
Regarding claim 7, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 1, wherein the laser emitter further comprises a suction part configured to support the substrate in a process of emitting the femtosecond pulse laser (KIM’s Para [0029 & 0032]).
Regarding claim 8, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 1, wherein the laser emitter comprises a laser irradiating part, which is configured to irradiate the femtosecond pulse laser to the first surface of the substrate and move on the substrate in a direction parallel to the first surface of the substrate (KIM’s Fig. 2-3 and ZENG’s Para [0006 & 0014]).
Regarding claim 9, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 8, wherein the laser irradiating part is configured to remove 5 um or less of a thickness of the substrate (ZENG’s femtosecond laser once incorporated into KIM’s device would be capable of removing 5 um or less of a thickness of the substrate). Notwithstanding, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 11, KIM teaches a semiconductor device fabrication apparatus, comprising:
a transferer (6, 70 & 14) configured to transfer a substrate 11, the substrate having a first surface (bottom surface of wafer 11) on which a circuit pattern (note components 15 &19 in Fig. 4B) is provided and a second surface (e.g. top of wafer 11) opposed to the first surface (Fig. 2-3 & Fig 4A-4B);
a grinder (e.g. Section B & Section C) comprising a first grinding part (section B) and a second grinding part (section C) and a polishing part (section D), each of the first grinding part and the second grinding part configured to grind the second surface of the substrate transferred by the transferer, and the polishing part configured to polish the second surface of the substrate that has been ground (Fig. 2-4B and associated text);
a laser emitter (78a-78d, Fig. 2) configured to emit a laser pulse to the second surface (top surface) of the substrate 11 transferred from the grinder (Para [0056]), while a protective tape 21 attached to the first surface of the substrate (Fig. 4A-4B);
a controller 74 configured to control an operation of the polishing part (Fig. 2); and
a mount (4c or 4b) configured to receive the substrate transferred from the laser emitter (78a-78d),
wherein the first grinding part (section B) is configured to perform a first grinding process on the second surface of the substrate 11 introduced into the grinder (Fig. 2 and associated text),
the second grinding part (section C) is configured to perform a second grinding process on the second surface of the substrate on which the first grinding process has been performed (Fig. 2 and associated text), and
the laser emitter is configured to emit the laser pulse to the second surface of the substrate on which the first grinding process and the second grinding process have been performed.
Kim is silent on (i) wherein the laser emitter is a femtosecond pulse laser; and (ii) wherein the mount is configured to attach a die attach film to the first surface of the substrate.
ZENG teaches in Para [0014] (i) a wafer processing apparatus comprising a laser emitter that emits femtosecond laser pulse. This has the advantage of providing extremely short pulses for extremely precise scanning and imaging and/or allowing to study ultrafast molecular dynamics and create micro-scale structures while avoiding damage to surrounding areas of the semiconductor wafer. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of KIM with the femtosecond laser, as taught by ZENG, so as to deliver intense energy in tiny bursts to obtain enhanced imaging/scanning while avoiding damage to surrounding areas of the semiconductor wafer.
Kawashima teaches (ii) a semiconductor device fabrication apparatus comprising a mount 20 configured to attach a die attach film 25 to a first surface of the substrate 12 (Fig. 1-Fig. 2b and associated text). This has the advantage of providing adhesion on wafer surface during die bonding operation. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of KIM and ZENG with the die attach film (DAF), as taught by Kawashima, so as to provide adhesion for a semiconductor wafer/die surface during a die bonding operation.
Regarding claim 12, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 11, wherein when the controller 74 controls the polishing part to not operate, the laser emitter is configured to emit the femtosecond pulse laser to the second surface of the substrate on which the second grinding process has been performed (KIM’s Fig. 2-3 and ZENG’s Para [0006 & 0014]).
Regarding claim 13, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 12, wherein the laser emitter is configured to remove at least a portion of the substrate by emitting the femtosecond pulse laser to the second surface of the substrate in a state in which the polishing part and the substrate are not in direct contact with each other (KIM’s Fig. 2-3 and ZENG’s Para [0006 & 0014]: the combination of KIM and ZENG’s device is capable of said functionality).
Regarding claim 14, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 11, wherein when the controller 74 controls the polishing part to operate, the polishing part is configured to polish the second surface of the substrate on which the second grinding process has been performed, and the laser emitter is configured to emit the femtosecond pulse laser to the second surface of the substrate that has been polished (KIM’s Fig. 2-3 and ZENG’s Para [0006 & 0014]).
Regarding claim 15, the combination of KIM, ZENG and Kawashima teaches the semiconductor device fabrication apparatus of claim 11, wherein the laser emitter comprises a laser irradiating part, which is configured to irradiate a laser in a shape of a line beam to the second surface of the substrate and move a plurality of times in a direction parallel to the second surface of the substrate to remove at least a portion of the substrate (ZENG’s femtosecond laser emitter once incorporated into KIM’s device would be capable said functionality).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over KIM, ZENG and Kawashima as applied to claim1 above, and further in view of HA (US Pub. 2019/0067059).
Regarding claim 6, the combination of KIM, ZENG and Kawashima is silent on the semiconductor device fabrication apparatus of claim 1, wherein a thickness of the substrate introduced into the laser emitter from the grinder is 70 um or less. However, HA teaches this widely known thickness for a semiconductor substrate in Para [0030]. These claim dimensions would have been obvious to one of the ordinary skill in the art in view of HA. One of the ordinary skill in the art is motivated to form device features as small as possible with large enough thickness to allow proper device operation, in order to save on material and processing costs. As such, it would have been obvious to use a thickness of 70 um or less for the semiconductor substrate.
The claim is prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir.1996)(claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955)(selection of optimum ranges within prior art general conditions is obvious).
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 04/20/2026 have been fully considered but they are not persuasive. The Examiner maintains that the prior art teaches the amended claims as addressed in the rejection above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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