The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al. (U.S. Patent Application Publication 2024/0038718, hereinafter referred to as Hung).
As to claim 1, Hung teaches 1. A semiconductor package, comprising: a first semiconductor chip [100 in Fig.4]; and a second semiconductor chip on the first semiconductor chip [200 in Fig.4], wherein the first semiconductor chip includes a first substrate, a plurality of through electrodes that penetrate the first substrate, a first wiring layer on a front side surface of the first substrate, first bonding pads [128 in Fig.4] on the first wiring layer and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first wiring layer, and a first passivation layer [124 in Fig.4] on the first wiring layer and that exposes at least portions of the first bonding pads and the first test pad, wherein the second semiconductor chip includes a second substrate, a second wiring layer on a front side surface of the second substrate, third bonding pads on the second wiring layer [228 in Fig.4], a second test pad on the second wiring layer, and a second passivation layer [224 in Fig.4] on the second wiring layer and that exposes at least portions of the third bonding pads and the second test pad, wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other, and wherein the first passivation layer and the second passivation layer are directly bonded to each other. [see ¶0067~0068 for example]
As to claim 2, Hung teaches 2. The semiconductor package of claim 1, wherein a distance of the first test pad from the front side surface of the first substrate is less than a distance of a first one of the first bonding pads from the front side surface of the first substrate. [¶0022]
As to claim 3, Hung teaches 3. The semiconductor package of claim 1, wherein the first and second test pads include aluminum or copper. [¶0028]
As to claim 4, Hung teaches 4. The semiconductor package of claim 1, wherein the first and second test pads include aluminum, and the first and second test pads are on the first and second wiring layers respectively. [¶0018]
As to claim 5, Hung teaches 5. The semiconductor package of claim 4, wherein the first and second test pads have a first thickness, and the first and third bonding pads have a second thickness greater than the first thickness. [¶0069]
As to claim 6, Hung teaches 6. The semiconductor package of claim 1, wherein the first and second test pads include copper, and the first and second test pads are provided in the first and second wiring layers respectively. [¶0020]
As to claim 7, Hung teaches 7. The semiconductor package of claim 1, wherein the first and second test pads have a first diameter, and the first and third bonding pads have a second diameter smaller than the first diameter. [¶0069]
As to claim 8, Hung teaches 8. The semiconductor package of claim 1, wherein the first and second passivation layers include silicon oxide, silicon nitride, or silicon carbon nitride. [¶0018]
As to claim 9, Hung teaches 9. The semiconductor package of claim l, wherein at least a portion of the first test pad and at least a portion of the second test pad are directly bonded to each other. [see Fig. 4]
As to claim 10, Hung teaches 10. The semiconductor package of claim 9, wherein the first test pad and the second test pad have a space therebetween that does not overlap the portion of the first test pad and the portion of the second test pad that are directly bonded to each other in a direction perpendicular to the first substrate. [see Fig. 4]
As to claim 11, Hung teaches 11. A semiconductor package, comprising: a first semiconductor chip including a first substrate having a first surface and a second surface opposite to the first surface, a plurality of through electrodes that penetrate the first substrate, first bonding pads on the first surface of the first substrate and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first surface of the first substrate, and a first passivation layer on the first surface of the first substrate and that exposes at least portions of the first bonding pads and the first test pad; and a second semiconductor chip on the first surface of the first semiconductor chip, the second semiconductor chip including a second substrate having a third surface and a fourth surface opposite to the third surface, third bonding pads on the third surface of the second substrate, a second test pad on the third surface of the second substrate, and a second passivation layer on the third surface of the second substrate and that exposes at least portions of the third bonding pads and the second test pad, wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other, wherein the first passivation layer and the second passivation layer are directly bonded to each other, and wherein the first and second test pads have a first diameter, and the first and third bonding pads have a second diameter that is smaller than the first diameter. [see 100, 200, 124, 128, 224, 228 in Fig.4 and ¶0067~0068 for example]
As to claim 12, Hung teaches 12. The semiconductor package of claim 1l, wherein the first and second test pads include aluminum or copper. [¶0028]
As to claim 13, Hung teaches 13. The semiconductor package of claim 11, wherein the first and second test pads include aluminum, and wherein the first and second test pads are in the first and second passivation layers respectively. [¶0018]
As to claim 14, Hung teaches 14. The semiconductor package of claim 13, wherein the first and second test pads have a first thickness, and the first and third bonding pads have a second thickness greater than the first thickness. [¶0069]
As to claim 15, Hung teaches 15. The semiconductor package of claim 11, wherein the first and second test pads include copper, and the first and second test pads are in first and second wiring layers under the first and second passivation layers respectively. [¶0069]
As to claim 16, Hung teaches 16. The semiconductor package of claim11, wherein the first and second passivation layers include silicon oxide, silicon nitride, or silicon carbon nitride. [¶0018]
As to claim 17, Hung teaches 17. The semiconductor package of claim 11, wherein at least a portion of the first test pad and at least a portion of the second test pad are directly bonded to each other. [see Fig. 4]
As to claim 18, Hung teaches 18. The semiconductor package of claim 17, wherein the first test pad and the second test pad have a space therebetween that does not overlap the portion of the first test pad and the portion of the second test pad that are directly bonded to each other in a direction perpendicular to the first substrate. [see Fig. 4]
As to claim 19, Hung teaches 19. The semiconductor package of claim 11, wherein the first test pad is electrically connected to a respective one of plurality of through electrodes, and the second test pad is electrically connected to a respective one of the third bonding pads. [see Fig. 4]
As to claim 20, Hung teaches 20. A semiconductor package, comprising: a package substrate; a first semiconductor chip including a first substrate having a first surface and a second surface opposite to the first surface, a plurality of through electrodes that penetrate the first substrate, first bonding pads on the first surface of the first substrate and electrically connected to respective ones of the plurality of through electrodes, second bonding pads on the second surface and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first surface of the first substrate, and a first passivation layer on the first surface of the first substrate and that exposes at least portions of the first bonding pads and the first test pad, wherein the first semiconductor chip is on the package substrate with conductive bumps therebetween that are on the second bonding pads; and a second semiconductor chip including a second substrate having a third surface and a fourth surface opposite to the third surface, third bonding pads on the third surface of the second substrate, a second test pad on the third surface of the second substrate and a second passivation layer on the third surface of the second substrate and that exposes at least portions of the third bonding pads and the second test pad, wherein the second semiconductor chip is on the first semiconductor chip such that the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip,wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other, and wherein the first passivation layer and the second passivation layer are directly bonded to each other. [see rejections above]
Conclusion
Claims 1-20 are rejected as explained above.
The prior art made of record in the PTO-892 form and not relied upon is considered pertinent to applicant's disclosure.
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/JAEHWAN OH/
Primary Examiner, Art Unit 2899