DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negate(32 of Hsu)d by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fischer(USPGPUB DOCUMENT: 2011/0133259, hereinafter Fischer) in view of Hsu (USPGPUB DOCUMENT: 2024/0203785, hereinafter Hsu).
Re claim 1 Fischer discloses a semiconductor device, comprising: a transistor[0053] including a gate(32 of Hsu); a dielectric layer(154) over the gate(32 of Hsu);
Fischer does not discloses a cavity in the dielectric layer(154) above the gate(32 of Hsu), a first portion of the cavity over the gate(32 of Hsu) having a negative sloped sidewall in the dielectric layer(154).
Hsu discloses in Fig 1G a cavity(P1/n1/P2/TP of Hsu) in the dielectric layer(42/36 of Hsu)[0020] above the gate(32 of Hsu), a first portion of the cavity over the gate(32 of Hsu) having a negative sloped sidewall (see Fig 1G of Hsu) in the dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Hsu to the teachings of Fischer in order to reduce the parasitic capacitance [0005, Hsu].
Re claim 2 Fischer and Hsu disclose the semiconductor device of claim 1, wherein the first portion of the cavity (P1/n1/P2/TP of Hsu) in the dielectric layer(154) has a first width at a first height and a second width less than the first width at a second height, wherein the first height is closer to the gate(32 of Hsu) than the second height and the negative sloped sidewall extends between the first height and the second height.
Re claim 3 Fischer and Hsu disclose the semiconductor device of claim 2, wherein the cavity (P1/n1/P2/TP of Hsu) has a second portion in the dielectric layer(154) over and contiguous with the first portion, the second portion having the second width at the second height and a third width larger than the second width at a third height, wherein the second height is between the first height and the third height.
Re claim 4 Fischer and Hsu disclose the semiconductor device of claim 3, wherein the cavity (P1/n1/P2/TP of Hsu) has a third portion in the dielectric layer(154) under and contiguous with the first portion, the third portion having a fourth width smaller than the first width at a fourth height below the first height.
Re claim 5 Fischer and Hsu disclose the semiconductor device of claim 2, wherein the cavity (P1/n1/P2/TP of Hsu) has a second portion in the dielectric layer(154) under and coupled to the first portion, the second portion having a third width at a third height, the third width smaller than the first width.
Re claim 6 Fischer and Hsu disclose the semiconductor device of claim 1, wherein the first portion has a trapezoidal (since the cavity in P1/n1 is a quadrilateral with parallel sides, this may be interpreted as trapezoidal) cross-section having a first width at a lower end of the first portion and a second width smaller than the first width at an upper end of the first portion.
Re claim 7 Fischer and Hsu disclose the semiconductor device of claim 6, wherein the cavity (P1/n1/P2/TP of Hsu) further includes a second portion in the dielectric layer(154) having a trapezoidal (since the cavity in 56/58 surrounding 60 of Hsu is a quadrilateral with two parallel sides, this may be interpreted as trapezoidal) cross-section having the second width at a lower end of the second portion contiguous with the upper end of the first portion and a third width larger than the second width at an upper end of the second portion.
Re claim 8 Fischer and Hsu disclose the semiconductor device of claim 7, wherein the cavity (P1/n1/P2/TP of Hsu) further includes a third portion in the dielectric layer(154) having a rectangular cross-section having a fourth width smaller than the first width of the first portion and contiguous with the lower end of the first portion.
Re claim 9 Fischer and Hsu disclose the semiconductor device of claim 1, wherein the negative sloped sidewall in the dielectric layer(154) includes a dopant in the dielectric layer(154).
Re claim 10 Fischer and Hsu disclose the semiconductor device of claim 1, wherein a portion of the dielectric layer(154) is positioned between the cavity (P1/n1/P2/TP of Hsu) and the gate(32 of Hsu).
Re claim 11 Fischer and Hsu disclose the semiconductor device of claim 1, wherein the cavity (P1/n1/P2/TP of Hsu) includes one of a gas[0056 of Hsu] and a vacuum therein.
Re claim 12 Fischer discloses a semiconductor device, comprising: a transistor[0053] including a gate(32 of Hsu); a dielectric layer(154) over the gate(32 of Hsu);
Fischer does not discloses a cavity in the dielectric layer(154) above the gate(32 of Hsu), the cavity comprising an air-gap and including: a first portion having a trapezoidal (since the cavity in 56/58 surrounding 60 of Hsu is a quadrilateral with two parallel sides, this may be interpreted as trapezoidal) cross-section having a first width at a lower end of the first portion and a second width smaller than the first width at an upper end of the first portion, and a second portion above the first portion, wherein the second portion has a trapezoidal cross-section having the second width at a lower end of the second portion and contiguous with the upper end of the first portion and a third width larger than the second width at an upper end of the second portion.
Hsu discloses in Fig 1G a cavity (P1/n1/P2/TP of Hsu) in the dielectric layer(42/36 of Hsu)[0020] above the gate(32 of Hsu), the cavity comprising an air-gap and including: a first portion(P1/n1 of Hsu) having a trapezoidal (since the cavity in P1/n1 is a quadrilateral with parallel sides, this may be interpreted as trapezoidal) cross-section having a first width at a lower end of the first portion and a second width smaller than the first width at an upper end (upper end of P1/n1 is smaller) of the first portion, and a second portion(P2/TP of Hsu) above the first portion, wherein the second portion has a trapezoidal (since the cavity in P2/TP is a quadrilateral with parallel sides, this may be interpreted as trapezoidal) cross-section having the second width at a lower end of the second portion and contiguous with the upper end of the first portion and a third width larger than the second width at an upper end of the second portion(since the top half of P2/TP is wider than the bottom of P2/TP, this may be interpreted as a third width larger than the second width at an upper end of the second portion).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Hsu to the teachings of Fischer in order to reduce the parasitic capacitance [0005, Hsu].
Re claim 13 Fischer and Hsu disclose the semiconductor device of claim 12, wherein the cavity (P1/n1/P2/TP of Hsu) further includes a third portion in the dielectric layer(154) having a rectangular cross-section having a fourth width smaller than the first width of the first portion and contiguous with the lower end of the first portion.
Re claim 14 Fischer and Hsu disclose the semiconductor device of claim 12, wherein the dielectric layer(154) defining the first portion of the cavity (P1/n1/P2/TP of Hsu) includes a dopant in the dielectric layer(154).
Response to Arguments
Applicant’s arguments with respect to claim 1-14 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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