DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (claims 1-14) and Species A (Fig 2., claims 1-4, 6-11, 13, 14) in the reply filed on 12/12/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
In addition, since claim 6 depends from non-elected claim 5, it is not being examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WO Publication No. 2021/176996 (Katsuhiko), cited by Applicant.
Katsuhiko discloses (Figs. 10, 11)
1. A semiconductor device, comprising:
a semiconductor element 10A;
a top electrode 11 on an upper surface of the semiconductor element 10A; and
a conductive metal plate 30 containing copper as a main component ([0040]) and solid-phase diffusion (see MPEP 2113 product-by-process language) bonded ([0020]) to the top electrode 11 of the semiconductor element 10A.
Katsuhiko discloses ([0020]-[0022])
2. The semiconductor device according to claim 1,
wherein the top electrode 11 includes a laminated structure obtained by laminating (see MPEP 2113 product-by-process language), in this order, an Au layer 112, an Ni layer 113, and an Al layer or an AISi layer 111 from a surface to which the conductive metal plate 30 is solid-phase diffusion bonded (see MPEP 2113 product-by-process language).
Katsuhiko discloses ([0040])
8. The semiconductor device according to claim 1,
wherein the conductive metal plate 30 is 0.01 mm to 1.0 mm thick.
Katsuhiko discloses ([0017], may be divided into a plurality of regions)
9. The semiconductor device according to claim 1, comprising
a plurality of top electrodes on the upper surface of the semiconductor element 10A, and a plurality of conductive metal plates on the respective top electrodes, the plurality of top electrodes including the top electrode 11, the plurality of conductive metal plates including the conductive metal plate 30.
Katsuhiko discloses ([0017], may be divided into a plurality of regions)
10. The semiconductor device according to claim 1,
wherein the conductive metal plate 30 is solid-phase diffusion (see MPEP 2113 product-by-process language) bonded to the top electrode 11 of the semiconductor element 10A at a plurality of portions.
Katsuhiko discloses ([0039], [0061])
11. The semiconductor device according to claim 1, comprising
a metal wire 53 solid-phase diffusion (see MPEP 2113 product-by-process language) bonded to the conductive metal plate 30, the metal wire 53 containing a material identical to a material of the conductive metal plate 30.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 4 is/are rejected under 35 U.S.C. 103 as being obvious over Katsuhiko as applied to claims 1 and 2 above, and further in in view of WO Publication No. 2018/167925 (Fujita), cited by Applicant.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Katsuhiko fails to disclose
3. The semiconductor device according to claim 2,
wherein the top electrode is formed on an interlayer insulating film, and the semiconductor device comprises a barrier metal between the interlayer insulating film and the Al layer or the AISi layer in the top electrode, the barrier metal containing Ti or W.
Fujita teaches (Figs. 1, 3, 5, 12, [0050]-[0052])
A semiconductor device comprising:
wherein the top electrode 26 / 20a / 31 / 20b / 20c is formed on an interlayer insulating film 24, and further comprising a barrier metal 26 between the interlayer insulating film 24 and the Al layer or the AISi layer 14a / 14b in the top electrode 26 / 20a / 31 / 20b / 20c, the barrier metal 26 containing Ti or W.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an interlayer insulating film and a barrier metal layer in Katsuhiko. The motivation would be to partially cover the aluminum layer and prevent a diffused impurity, respectively which is well-known in the semiconductor art as discussed in Fujita. See MPEP 2144.03.
Katsuhiko discloses ([0081]-[0084]) / Fujita teaches ([0072]-[0077])
4. The semiconductor device according to claim 3,
wherein the Au layer is 30 nm to 70 nm thick, the Ni layer is 2 µm to 15 µm thick, the Al layer or the AlSi layer is 3 µm to 10 µm thick, and the barrier metal is 10 nm to 300 nm thick.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko as applied to claim 1 above, and further in view of JP Publication No. 2021-093473 (Kanda), cited by Applicant.
Katsuhiko fails to disclose
7. The semiconductor device according to claim 1,
wherein the conductive metal plate is smaller in plane size than the top electrode, the conductive metal plate being positioned without extending beyond the top electrode.
Kanda teaches (Fig. 4)
A semiconductor device comprising:
wherein the conductive metal plate 3 is smaller in plane size than the top electrode 121 / 11 / 123, the conductive metal plate 3 being positioned without extending beyond the top electrode 121 / 11 / 123.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a conductive metal plate smaller than the top electrode in Katsuhiko. The motivation would be to more reliably protect the semiconductor element, thus attaining low resistance of a conduction route as taught by Kanda. This configuration would also be a matter of routine engineering design considerations. See MPEP 2144.04.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2017/0271239 (Morozumi).
Katsuhiko fails to disclose
13. The semiconductor device according to claim 1,
wherein the semiconductor element is a reverse-conducting insulated gate bipolar transistor.
Morozumi teaches ([0063], [0078])
A semiconductor device comprising:
wherein the semiconductor element 11 / 511 is a reverse-conducting insulated gate bipolar transistor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a RC-IGBT in Katsuhiko. The motivation would be based on its suitability for the intended purpose as discussed in Morozumi. See MPEP 2144.07.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Katsuhiko as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2015/0001692 (Tsai).
Katsuhiko fails to disclose
14. The semiconductor device according to claim 1,
wherein the semiconductor element contains a wide-bandgap semiconductor.
Tsai teaches ([0038])
A semiconductor device comprising:
wherein the semiconductor element 11 contains a wide-bandgap semiconductor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a wide-bandgap semiconductor in Katsuhiko. The motivation would be based on its suitability for the intended purpose as discussed in Tsai. See MPEP 2144.07.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2007/0215996 (Otremba), 2019/0122998 (Hino), 2023/0395550 (Fukui) teach a semiconductor device including a laminated top electrode and a conductive plate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893