Office Action Predictor
Last updated: April 15, 2026
Application No. 18/359,123

SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Jul 26, 2023
Examiner
DOAN, THERESA T
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mediatek INC.
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
1y 10m
To Grant
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
791 granted / 896 resolved
+20.3% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
24 currently pending
Career history
920
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
42.1%
+2.1% vs TC avg
§102
38.4%
-1.6% vs TC avg
§112
3.3%
-36.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 896 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (2014/0225192). Regarding claim 1, Lee (Fig. 1) discloses a semiconductor device, comprising: a substrate 10 having an active region 11 ([0020]); a gate strip 15 disposed on the substrate 10 within the active region 11, wherein the gate strip 15 extends along a first direction ([0020]); a source doped region 18 located in the active region 11 and adjacent to a first side of the gate strip 15 along the first direction; and a body doped region 132/13 located in the active region 11 and adjacent to the first side of the gate strip 15, wherein the body doped region 132 (P+ type) and the source doped region 18 (N+ type) have opposite conductivity types, wherein the body doped region 132 has a first length along a second direction that is different from the first direction, wherein the first length gradually changes along the first direction (Fig. 1 and [0020]). Regarding claim 4, Lee (Fig. 1) discloses wherein the body doped region 132 is disposed adjacent to the source doped region 18 along the first direction. Regarding claim 20, Lee (Fig. 1) discloses further comprising: a drain doped region 19 located in the active region 11 and adjacent to a second side of the gate strip 15 along the first direction, wherein the first side is opposite to the second side ([0020]). Allowable Subject Matter Claims 2-3 and 5-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record fails to disclose all the limitations recited in the above claims. Specifically, the prior art of record fails to disclose wherein the body doped region has a center portion located between two end portions along the first direction, wherein the body doped region is tapered from the center portion to the two end portions (claim 2); or wherein the body doped region or the source doped is tapered toward to the gate strip along the second direction (claims 5 and 15); or wherein the body doped region has a first width along the first direction, wherein the first width gradually changes along the second direction (claim 6); or wherein the source doped region has a second width along the first direction, wherein the second width gradually changes along the second direction (claim 16). Claims 21-32 are allowed. The following is an examiner's statement of reasons for allowance: The prior art of record neither anticipates nor renders obvious all the limitations in the base claims 21 and 30. Specifically, the combination of a semiconductor device, comprising: a body doped region of the first conductivity type located in the active region and adjacent to the first side of the first gate strip, wherein the body doped region has least one edge close to the first side of the first gate strip, wherein an extended line of the edge of the body doped region meets the first side of the first gate strip, and wherein an angle between the extended line and the first side of the first gate strip is an acute angle (claim 21) or the combination of the semiconductor device, comprising: a body doped region of the first conductivity type disposed in the active region and adjacent to the first side of the gate strip, wherein ratios of widths of the body doped region to widths of the source doped region in cross-sectional views in the first direction are gradually increased along a direction away from the first gate strip (claim 30). The dependent claims being further limiting and definite are also allowable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THERESA T DOAN whose telephone number is (571)272-1704. The examiner can normally be reached on Monday, Tuesday, Wednesday and Thursday from 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THERESA T DOAN/ Primary Examiner, Art Unit 2814
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Prosecution Timeline

Jul 26, 2023
Application Filed
Dec 11, 2025
Non-Final Rejection — §102
Apr 03, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598750
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 07, 2026
Patent 12593718
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2y 5m to grant Granted Mar 31, 2026
Patent 12593636
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE
2y 5m to grant Granted Mar 31, 2026
Patent 12588511
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2y 5m to grant Granted Mar 24, 2026
Patent 12588527
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2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+5.1%)
1y 10m
Median Time to Grant
Low
PTA Risk
Based on 896 resolved cases by this examiner. Grant probability derived from career allow rate.

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